C64DX SYSTEM SPECIFICATION o Design Concepts o Hardware Specifications o Software Specifications Requires ROM Version 0.9A.910228 or later. COPYRIGHT 1991 COMMODORE BUSINESS MACNINES, INC. ALL RIGHTS RESERVED. INFORMATION CONTAINED HEREIN IS THE UNPUBLISHED AND CONFIDENTIAL PROPERTY OF COMMODORE BUSINESS MACHINES, INC. USE, REPRODUCTION, OR DISCLOSURE OF THIS INFORMATION WITHOUT THE PRIOR WRITTEN PERMISSION OF COMMODORE IS PROHIBITED. CCCC 666 555555 C C 6 5 C 6 5 C 6 55555 C 66666 5 5 C 6 6 5 C 6 6 5 C C 6 6 5 5 CCCC 6666 5555 Copyright 1991 Commodore Business Machines, Inc. All Rights Reserved. This documentation contains confidential, proprietary, and unpublished information of Commodore Business Machines, Inc. The reproduction, dissemination, disclosure or translation of this information to others without the prior written consent of Commodore Business Machines, Inc. is strictly prohibited. Notice is hereby given that the works of authorship contained herein are owned by Commodore Business Machines, Inc. pursuant to U.S. Copyright Law, Title 17 U.S.C. 3101 et. seq. This system specification reflects the latest information available at this time. Updates will occur as the system evolves. Commodore Business Machines, Inc. makes no warranties, expressed or implied with regard to the information contained herein including the quality, performance, merchantability, or fitness of this information or the system as described. This system specification contains the contributions of several people including: Fred Bowen, Paul Lassa, Bill Gardei, and Victor Andrade. Portions of the BASIC ROM code are Copyright 1977 Microsoft. PPPP RRRR EEEE L I M M I N N A RRRR Y Y P P R R E L I MM MM I NN N A A R R Y Y PPPP RRRR EEE L I M M M I N N N AAAAA RRRR Y P R R E L I M M I N NN A A R R Y P R R EEEE LLLL I M M I N N A A R R Y Revision 0.2 (pilot release) January 31, 1991 At this time, Pilot Production, the C65 system consists of either revision 2A or 2B PCB, 4510R3, 4567R5 (PAL only), F011B/C FDC, and 018 DMAgic chips. There will be changes to all these chips before Production Release. This work is by: Fred Bowen System Software - C65 Paul Lassa Hardware engineer - C65, DMagic Bill Gardei LSI engineer - 4567, FDC Victor Andrade LSI engineer - 4510 Included are contributions by contractors hired by Commodore for the C65 project. These contributions include the DOS, Graphics, Audio, and Memory management areas. Several 4502 assembler systems are available: VAX, Amiga, and PC based BSO-compatible cross assemblers. PC based custom cross assembler by Memocom, compatible with Memocom 4502 emulator and Mem-ulator systems. C128-based BSO compatible cross assembler by Commodore. Custom software support is available for the following logic analyzers: Hewlett Packard HP655x A and B logic analyzers. Table of Contents ----------------- 1.0. Introduction 1.1. System Concept 1.2. System Overview 1.3. System Components 1.4. System Concerns 1.4.1. C64 Compatibility 1.4.1.1. Software 1.4.1.2. Hardware 1.4.2. 1581 DOS Compatibility 1.4.3. Modes of Operation 1.5. System Maps 1.5.1. Composite System Memory Map 1.5.2. C65 System Memory Map 1.5.3. C65 System Memory Layout 1.5.4. C65 I/O Memory Map 2.0. System Hardware 2.1. Keyboard 2.1.1. Keyboard Layout 2.1.2. Keyboard Matrix 2.2. External Ports & Form-Factor 2.3. Microcontroller 2.3.1. Description 2.3.2. Configuration 2.3.3. Functional Description 2.3.3.1. Pin Description 2.3.3.2. Timing Description 2.3.3.3. Register Description 2.3.4. Mapper 2.3.5. Peripheral Control 2.3.5.1. I/O Ports 2.3.5.2. Handshaking 2.3.5.3. Timers 2.3.5.4. TOD Clocks 2.3.5.5. Serial Ports 2.3.5.6. Fast Serial Ports 2.3.5.7. Interrupt Control 2.3.5.8. Control Registers 2.3.6. UART 2.3.6.1. Control Registers 2.3.6.2. Status Register 2.3.6.3. Character Configuration 2.3.6.4. Register Map 2.3.7. CPU 2.3.7.1. Introduction 2.3.7.2. CPU Operation 2.3.7.3. Interrupt Handling 2.3.7.4. Addressing Modes 2.3.7.5. Instruction Set 2.3.7.6. Opcode Table 2.4. Video Controller 2.4.1. Description 2.4.2. Configuration 2.4.3. Functional Description 2.4.4. Programming 2.4.5. Registers 2.5. Disk Controller 2.5.1. Description 2.5.2. Configuration 2.5.3. Registers 2.5.4. Functional Description 2.5.5. Expansion port protocol 2.5.6. Timing diagrams 2.6. Expansion Disk Controller (option) 2.6.1. Description 2.6.2. Expansion port protocol 2.7. DMAgic Controller 2.7.1. Description 2.7.2. Registers 2.8. RAM Expansion Controller (option) 2.8.1. Description 2.9. Audio Controller 3.0. System Software 3.1. BASIC 10.0 3.1.1. Introduction 3.1.2. List of Commands 3.1.3. Command Descriptions 3.1.4. Variables 3.1.5. Operators 3.1.6. Error Messages 3.1.6.1. BASIC Error Messages 3.1.6.2. DOS Error Messages 3.2. Monitor 3.2.1. Introduction 3.2.2. Commands and Conventions 3.2.3. Command Descriptions 3.3. Editor 3.3.1. Escape Sequences 3.3.2. Control Characters 3.4. Kernel 3.4.1. Kernel Jump Table 3.4.2. BASIC Jump Table 3.4.3. Editor Jump Table 3.4.4. Indirect Vectors 3.4.5. Kernel Documentation 3.4.6. BASIC Math Package Documentation 3.4.7. I/O Devices 3.5. DOS 3.6. RS-232 4.0. Development Support 1.0. Introduction This specification describes the requirements for a low-cost 8-bit microcomputer system with excellent graphic capabilities. 1.1. System Concept The C65 microcomputer is a low-cost, versatile, competitive product designed for the international home computer and game market. The C65 is well suited for first time computer buyers, and provides an excellent upgrade path for owners of the commercially successful C64. The C65 is composed of concepts inherent in the C64 and C128. The purpose of the C65 is to modernize and revitalize the 10 year old C64 market while still taking advantage of the developed base of C64 software. To accomplish this, the C65 will provide a C64 mode of operation, offering a reasonable degree of C64 software compatibility and a moderate degree of add-on hardware and peripheral compatibility. Compatibility can be sacrificed when it impedes enhanced functionality and expandability, much as the C64 sacrificed VIC-20 compatibility. It is anticipated that the many features and capabilities of the new C65 mode will quickly attract the attention of developers and consumers alike, thereby revitalizing the low-end home computer market. The C65 incorporates features that are normally found on today's more expensive machines, continuing the Commodore tradition of maximizing performance for the price. The C65 will provide many new opportunities for third party software and hardware developers, including telecommunications, video, instrument control (including MIDI), and productivity as well as entertainment software. 1.2. System Overview o CPU -- Commodore CSG4510 running at 1.02 or 3.5 Mhz o New instructions, including Rockwell and GTE extensions o Memory Mapper supporting up to 1 Megabyte address space o R6511-type UART (3-wire RS-232) device, programmable baud rate (50-56K baud, MIDI-capable), parity, word size, sync and async. modes. XD/RD wire ORed/ANDed with user port. o Two CSG6526-type CIA devices, each with 2 I/O ports programmable TOD clocks, interval timers, interrupt control o Memory o RAM -- 128K bytes (DRAM) Externally expandable from additional 512K bytes to 4MB using dedicated RAM expansion port. o ROM -- 128K bytes C64 Kernel and BASIC 2.2 C65 Kernel, Editor, BASIC 10.0, ML Monitor (like C128) DOS v10 (1581 subset) Multiple character sets: 40 and 80 column versions National keyboards/charsets for foreign language systems Externally expandable by conventional C64 ROM cartridges via cartridge/expansion port using C64 decodes. Externally expandable by additional 128K bytes or more via cartridge/expansion port using new system decodes. o DMA -- Custom DMAgic controller chip built-in Absolute address access to entire 8MB system map including I/O devices, both ROM & RAM expansion ports. List-based DMA structures can be chained together Copy (up,down,invert), Fill, Swap, Mix (boolean Minterms) Hold, Modulus (window), Interrupt, and Resume modes, Block operations from 1 byte to 64K bytes DRQ handshaking for I/O devices Built-in support for (optional) expansion RAM controller o Video -- Commodore CSG 4567 enhanced VIC chip o RGBA with sync on all colors or digital sync o Composite NTSC or PAL video, separate chroma/luma o Composite NTSC or PAL digital monochrome o RF TV output via NTSC or PAL modulator o Digital foreground/background control (genlock) o All original C64 video modes: 40x25 standard character mode Extended background color mode 320x200 bitmap mode Multi-color mode 16 colors 8 sprites, 24x21 o 40 and 80 character columns by 25 rows: Color, blink, bold, inverse video, underline attributes o True bitplane graphics: 320 x 200 x 256 (8-bitplane) non-interlaced 640 x 200 x 16* (4-bitplane) non-interlaced 1280 x 200 x 4* (2-bitplane) non-interlaced 320 x 400 x 256 (8-bitplane) interlaced 640 x 400 x 16* (4-bitplane) interlaced 1280 x 400 x 4* (2-bitplane) interlaced *plus sprite and border colors o Color palettes: Standard 16-color C64 ROM palette Programmable 256-color RAM palette, with 16 intensity levels per primary color (yielding 4096 colors) o Horizontal and vertical screen positioning verniers o Display Address Translator (DAT) allows programmer to access bitplanes easily and directly. o Access to optional expansion RAM o Operates at either clock speed without blanking o Audio -- Commodore CSG8580 SID chips o Stereo SID chips: Total of 6 voices, 3 per channel Programmable ADSR envelope for each voice Filter, modulation, audio inputs, potentiometer Separate left/right volume, filter, modulation control o Disk, Printer support -- o FDC custom MFM controller chip built in, with 512-byte buffer, sector or full track read/write/format, LED and motor control, copy protection. o Built-in 3.5" double sided, 1MB MFM capacity drive o Media & file system compatible with 1581 disk drive o Supports one additional "dumb" drive externally. o Standard CBM bus serial (all modes, about 4800 baud) o Fast serial bus (C65 mode only, about 20K baud) o Burst serial (C65 mode only, about 50K baud) o External ports -- o 50-pin Cartridge/expansion port (ROM cartridges, etc.) o 24-pin User/parallel port (modem (1670), RS-232 serial) o Composite video/audio port (8-pin DIN) o Analog RGB video port (DB-9) o RF video output jack o Serial bus port (disks (1541/1571/1581), printers, etc.) o External floppy drive port (mini DIN8) o 2 DB9 control ports (joystick, mouse, tablets, lightpen) o Left and right stereo audio output jacks o RAM expansion port, built-in support for RAM controller o Keyboard -- 77 keys, including standard C64 keyboard plus: o Total of 8 function keys, F1-F16, shifted and nonshifted o TAB, escape, ALT, CAPS lock, no scroll, help (F15/16) o Power, disk activity LEDs o Power supply -- external, brick type o +5VDC at 2.2A and +12VDC at .85A 1.3. System Components Microcontroller: 4510 (65CE02, 2x6526, 6511 UART, Mapper, Fast serial) Memory: 4464 DRAM (128K bytes) 271001 ROM (128K bytes) Video controller: 4567 (extended VIC, DAT, PLA) Audio controllers: 6581 (SID) Memory control: 41xx-F018 (DMA) Disk controller: 41xx-F011 (FDC, supports 2 DSDD drives, MFM, RAM buffer) KEYS + USER PORT | + CONTROL PORTS EXPANSION PORT | | + + + + +---+ | | | | | | | | +MOD-> RFOUT ++-+-++ | | | | +-+----> COMP,CHROMA/LUMA | | | | | | +------> RGBA | +-------------------------------------+------+ | +---+ | +--------------------------------------------+ +--...-+ R +--+ | | | | | | E | EXPANSION | | +---+ +---+ +---+ +---+ +---+ | | | +--...-+ C +--+ MEMORY | 4 | | | | | | | | | | | | | | 4 | +---+ | 5 +-----+ D +--+ F +--+ S +--+ S +--+ R +-+----+ 5 | +--+ +--+ +--+ +--+ | 1 +-----+ M +--+ D +--+ I +--+ I +--+ O +------+ 6 | | | | | | | | | | 0 | ADR | A | | C | | D | | D | | M | | | 7 +--+ +--+ +--+ +--+ | | | | G | | | | | | | | | | | +--+ +--+ +--+ +--+ | | +-----+ I +--+ +--+ +--+ +--+ +---+--+ +--+ +--+ +--+ +--+ | | +-----+ C +--+ +--+ +--+ +--+ +------+ +--+ +--+ +--+ +--+ | | | DAT | | | | | | | | | | | | | | | | | | | | +--+--+ +---+ +++-+ +-+-+ +-+-+ +---+ +---+ +--+ +--+ +--+ +--+ | || | | 128K + || R L RAM INTERNAL SERIAL BUS || SPEAKERS ++ FLOPPY PORT 1.4. System Concerns 1.4.1. C64 Compatibility Issues 1.4.1.1. Software C64 software compatibility is an important goal. To this end, when the system is in "C64 mode" the processor will operate at average 1.02MHz speed and dummy "dead" cycles are emulated by the processor. The C64 ROM is the same except for patches to serial bus routines in the kernel (to interface built-in drive), the removal of cassette code (there is no cassette port), and patches to the C64 initialization routines to boot C65 mode if there is no reason (eg., cartridges) to stay in C64 mode. Compatibility with C64 software that uses previously unimplemented 6502 opcodes (often associated with many copy-protection schemes) or that implements extremely timing dependent "fast loaders" is iherently impossible. Because the VIC-III timing is slightly different, programs that are extremely timing dependant may not work properly. Also because the VIC-III does not change display modes until the end of a character line, programs that change displays based strictly upon the raster position may not display things properly. The aspect ratio of the VIC-III display is slightly different than the VIC-II. The use of a 1541-II disk drive (optional) will improve compatibility. C64 BASIC 2.2 compatibility will be 100% (within hardware constraints). C128 BASIC 10 compatibility will be moderate (graphic commands are different, some command parameters different, and there are many new commands). 1.4.1.2. Hardware C64 hardware compatibility is limited. Serial bus and control port devices (mouse, joysticks, etc.) are fully supported. Some user port devices are supported such as the newer (4-DIP switch) 1670 modems, but there's no 9VAC so devices which require 9VAC won't function correctly. The expansion port has additional pins (50 total), and the pin spacing is closer than the C64 (it's like the PLUS/4). An adaptor ("WIDGET") will be necessary to utilize C64 cartridges and expansion port devices. Furthermore, timing differences between some C64 and C65 expansion port signals will affect many C64 expansion devices (such as the 1764). 1.4.2. DOS Compatibility The built-in C65 DOS is a subset of Commodore 1581 DOS. There is no track cache, index sensor, etc. To load and run existing 1541-based applications, the consumer must add a 1541 drive to the system. Many commercial applications cannot be easily ported from 1541/5.25" media to 1581/3.5" media, due to copy protection or "fast loaders". Most C64 applications that directly address DOS memory, specific disk tracks or sectors, or rely on DOS job queues and timing characteristics will not work with the built-in drive and new DOS. 1.4.3. Operating Modes The C65 powers up in the C64 mode. If there are no conditions present which indicate that C64 mode is desired, such as the C= key depressed or a C64 cartridge signature found, then C65 mode will be automatically brought into context. Unlike the C128, "C6 4 mode" is escapable. Like the C128, all of the extended features of the C65 system are accessible from "C64 mode" via custom software. Whenever the system initiates C64 mode, new VIC mode is always disabled except when the DOS is required. 1.5. System Maps 1.5.1. Composite System Memory Map C64 CARTRIDGES C64 C65 RAM-LO RAM-HI $FFFF+-----------+ +-----------+ +-----------+ +-----------+ +-----------+ | | | | | | | | |COLOR NYBS | $F800| GAME | | KERNEL | | KERNEL | | | +-----------+ | | | & | | & | | | | | | CARD | | EDITOR | | EDITOR | | | | | | | | | | | |.......... | | ......... | $E000+-----------+ +-----------+ +-----------+ | C65 EVEN | | C65 ODD | |COLOR NYBS | |COLOR NYBS | | BITPLANES | | BITPLANES | |I/O & CHARS| |I/O & CHARS| |.......... | | ......... | $D000 ------------ +-----------+ +-----------+ | | | | | | | | | | | KERNEL | | | | | | | | C65 BASIC | | C65 VARS &| $C000+-----------+ +-----------+ +-----------+ | TEXT | | STRINGS | | | | | | | |$2000-$FEFF| |$2000-$F7FF| |APPLICATION| | | | | | | | | | | | BASIC | | | | | | | | CARD _ HI | | | | BASIC | | | | | | | | | | GRAPHICS | | | | | $A000+-----------+ +-----------+ | | +-----------+ | | | | | | | | | | |APPLICATION| | DOS | | | | | | | | (MAPPED) | | | | | | CARD _ LOW| | | | | | | | | | | | C64 VARS &| | | $8000+-----------+ ------------- +-----------+ | STRINGS | | | |COLOR NYBS | | TEXT-$BFFF| | | |I/O & CHARS| | | | | $6000 -------------------------- +-----------+ | C64 BASIC | | | | | | TEXT | | | | | |$0800-VARS | | | | | | | | | | | | | | | | BASIC | | | | | | | | | | | | | | | | | | | | | | | $2000 -------------------------- +-----------+ +-----------+ +-----------+ | C65 SYSTEM| | C64 & C65 | |TEXTSCREENS| | DOS | $0000 ---------------------------------------- +-----------+ +-----------+ 1.5.2. C65 System Memory Map MAPPER BANK -----+----- | | 1M $F,FFFF +-------------+ ---------- | | +- -+ | RAM | 512K BLOCK APPEARING 768K $C,0000 +- -+ HERE IS DETERMINED BY | EXPANSION | THE RAM EXPANDER CTLR +- -+ (UP TO 8MB TOTAL MAP) | | 512K $8,0000 +-------------+ ---------- | | +- RESERVED -+ FUTURE CARTRIDGES | | 256K $4,0000 +-------------+ ---------- | SYSTEM ROMS | 128K $2,0000 +-------------+ SEE SYSTEM MEMORY | SYSTEM ROMS | LAYOUT, BELOW $0,0000 +-------------+ ---------- 1.5.3. C65 System Memory Layout BANK 0 BANK 1 BANK 2 BANK 3 RAM-LO RAM-HI ROM-LO ROM-HI $FFFF +-------------+ +-------------+ +-------------+ +-------------+ $F800 | | | COLOR NYBS | | C64 | | C65 | | | +-------------+ | KERNEL | | KERNEL | $E000 | BITPLANES | | | +-------------+ +-------------+ | (EVEN) | | | | C64 CHRSET | | | $D000 | | | BITPLANES | +-------------+ | RESERVED | | | | (ODD) | | INTERFACE | | | $C000 +.............+ +.............+ +-------------+ +-------------+ | | | | | C64 | | | | | | | | BASIC | | | $A000 | STRUCTURES | | STRINGS | +-------------+ | GRAPHICS | | ??? | | | | C65 | | | | | | | | CHRSET | | | $8000 +.............+ +.............+ +-------------+ +-------------+ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BASIC | | BASIC | | RESERVED | | C65 BASIC | | TEXT | | VARIABLES | | | | | | | | | | | | | | | | | | | | | $4000 | | | | +-------------+ | | | | | | | | | | | | | | | | | | | | | | | | | | $2000 +-------------+ +-------------+ | | +-------------+ | TEXT SCREEN | | DOS | | DOS | | MONITOR | +-------------+ | | | | | | | | | BUFFERS | | (MAPS TO | | (MAPS TO | | SYSTEM VARS | | & VARS | | $8000) | | $6000) | | | | | | | | | $0000 +-------------+ +-------------+ +-------------+ +-------------+ What does this mean? Here is what the 64K memory map looks like in various configurations (i.e., as seen by the processor): C64 mode: $E000-$FFFF Kernel, Editor, Basic overflow area --------- $D000-$DFFF I/O and Color Nybbles, Character ROM $C000-$CFFF Application RAM $A000-$BFFF BASIC 2.2 $0002-$9FFF RAMLO. VIC screen at $0400-$07FF BASIC program & vars from $0800-$9FFF C65 mode: $E000-$FFFF Kernel, Editor ROM code --------- $D000-$DFFF I/O and Color Bytes (CHRROM at $29000) $C000-$CFFF Kernel Interface, DOS ROM overflow area $8000-$BFFF BASIC 10.0 Graphics & Sprite ROM code $2000-$7FFF BASIC 10.0 ROM code $0002-$1FFF RAMLO. VIC screen at $0800-$0FFF BASIC prgs mapped from $02000-$0FF00 BASIC vars mapped from $12000-$1F7FF C65 DOS mode: $E000-$FFFF Kernel, Editor ROM code ------------- $D000-$DFFF I/O (CIA's mapped out), Color Bytes $C800-$CFFF Kernel Interface $8000-$C3FF DOS ROM code $2000-$7FFF (don't care) $0000-$1FFF DOS RAMHI C65 Monitor: $E000-$FFFF Kernel, Editor ROM code ------------ $D000-$DFFF I/O and Color Bytes $C000-$CFFF Kernel Interface $8000-$BFFF (don't care) $6000-$7FFF Monitor ROM code $0002-$5FFF RAMLO It's done this way for a reason. The CPU MAPPER restricts the programmer to one offset for each 32Kbyte half of a 64Kbyte segment. For one chunk of ROM to MAP in another chunk with a different offset, it must do so into the other half of memory from which it is executing. The OS does this by never mapping the chunk of ROM at $C000-$DFFF, which allows this chunk to contain the Interface/MAP code and I/O (having I/O in context is usually desirable, and you can't map I/O anyhow). The Interface/MAP ROM can be turned on and off via VIC register $30, bit 5 (ROM @ $C000), and therefore does not need to be mapped itself. Generally, OS functions (such as the Kernel, Editor, and DOS) live in the upper 32K half of memory, and applications such as BASIC or the Monitor) live in the lower 32K half. For example, when Monitor mode is entered, the OS maps out BASIC and maps in the Monitor. Each has ready access to the OS, but no built-in access to each other. When a DOS call is made, the OS overlays itself with the DOS (except for the magical $C000 code) in the upper 32K half of memory, and overlays the application area with DOS RAM in the lower 32K half of memory. 1.5.4. C65 System I/O Memory Map +-------------+ $DF00 | I/O-2 | EXTERNAL I/O SELECT $DE00 | I/O-1 | EXTERNAL I/O SELECT +-------------+ $DD00 | CIA-2 | SERIAL, USER PORT $DC00 | CIA-1 | KEYBOARD, JOYSTICK, MOUSE CONTROL +-------------+ $D800 | COLOR NYB | COLOR MATRIX (*FROM $1F800-$1FFFF) +-------------+ $D700 | DMA | *DMA CONTROLLER +-------------+ $D600 | UART | *RS-232, FAST SERIAL, NEW KEY LINES +-------------+ $D440 | SID (L) | AUDIO CONTROLLER (LEFT) $D400 | SID (R) | AUDIO CONTROLLER (RIGHT) +-------------+ $D300 | BLU PALETTE | $D200 | GRN PALETTE | *COLOR PALETTES (NYBBLES) $D100 | RED PALETTE | +-------------+ $D0A0 | REC | *RAM EXPANSION CTRL (OPTIONAL) +-------------+ $D080 | FDC | *DISK CONTROLLER +-------------+ $D000 | VIC-4567 | VIDEO CONTROLLER +-------------+ . . . +-------------+ $0000 | 4510 | MEMORY CONTROL FOR C64 MODE +-------------+ (this register is actually in the VIC-4567 in the C65) *NOTE: VIC must be in "new" mode to address these devices 2.0. C65 System Hardware 2.1.1. Keyboard Layout +----+ +----+----+----+----+ +----+----+----+----+ +----+----+----+----+ |RUN | |ESC |ALT |ASC | NO | | F1 | F3 | F5 | F7 | | F9 | F11| F13|HELP| |STOP| | | |DIN |SCRL| | F2 | F4 | F6 | F8 | | F10| F12| F14| | +----+ +----+----+----+----+ +----+----+----+----+ +----+----+----+----+ +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ | <- | ! | " | # | $ | % | & | ' | ( | ) | | | | |CLR |INST| | | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 0 | + | - | œ |HOME|DEL | +----+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+----+ | TAB | | | | | | | | | | | | | ã | RSTR | | | Q | W | E | R | T | Y | U | I | O | P | @ | * | ^ | | +----+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+------+ |CTRL|SHFT| | | | | | | | | | [ | ] | | RETURN | | |LOCK| A | S | D | F | G | H | J | K | L | : | ; | = | | +----+----+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+----+----+----+ | C= | SHIFT | | | | | | | | < | > | ? | SHIFT|CRSR| | | | Z | X | C | V | B | N | M | , | . | / | | UP | +----+-------+-+--+----+----+----+----+----+----+----+----+-+--+-+----+----+----+ | SPACE | |CRSR|CRSR|CRSR| | | |LEFT|DOWN|RITE| +--------------------------------------------+ +----+----+----+ Notes: 1/ The cursor keys are special -- the shifted cursor keys appear as separate keys, but in actuality pressing them generates a SHIFT plus the normal cursor code, making them totally compatible with, and therefore functional in, C64 mode. 2/ There are a total of 77 keys, two of which are locking keys. 3/ The NATIONAL keyboards are similar, and their layout and operation is identical to their C128 implementation. 2.1.2. Keyboard Matrix +-----+-----+-----+-----+-----+-----+-----+-----+-----+ +-----+ | C0 | C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 | | GND | |PIN20|PIN19|PIN18|PIN17|PIN16|PIN15|PIN14|PIN13|PIN-4| |PIN-1| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ +--+--+ | | | | | | | | | | | | | | | | | | | | V V V V V V V V V | +-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | R0 |<----+ INS | # | % | ' | ) | + | œ | ! | NO | | |PIN12| | DEL | 3 | 5 | 7 | 9 | | | 1 | SCRL| | +-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | R1 |<----+ RET | W | R | Y | I | P | * | <-- | TAB | | |PIN11| | | | | | | | | | | | +-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | R2 |<----+ HORZ| A | D | G | J | L | ] | CTRL| ALT | | |PIN10| | CRSR| | | | | | ; | | +----------+ | +-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | | R3 |<----+ F8 | $ | & | { | 0 | - | CLR | " | HELP| | | |PIN-9| | F7 | 4 | 6 | 8 | | | HOM | 2 | | | | +-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | | R4 |<----+ F2 | Z | C | B | M | > |RIGHT|SPACE| F10 | | | |PIN-8| | F1 | | | | | . |SHIFT| BAR | F9 | | | +-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | | R5 |<----+ F4 | S | F | H | K | [ | = | C= | F12 | | | |PIN-7| | F3 | | | | | : | | | F11 | | | +-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | | R6 |<----+ F6 | E | T | U | O | @ | ã | Q | F14 | | | |PIN-6| | F5 | | | | | | ^ | | F13 | | | +-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | | R7 |<----+ VERT|LEFT | X | V | N | < | ? | RUN | ESC +------+ | | |PIN-5| | CRSR|SHIFT| | | | , | / | STOP| +--+ | | | +-----+ +--+--+--+--+-----+-----+-----+-----+--+--+-----+-----+ | | | | | | | | | | | | | | | | | | | +--+--+ / (LOCKING) | | | | | | |SHIFT+----+ +------------------------------------+ | | | | | LOCK| | | | | | +-----+ | | | | | +-----+-----+ | | | +--+--+ | | | | | |CRSR +------------+-------------+ +---------------+ | | | UP | K1 PIN-21 | | | | +--+--+ | 4066 | | | | | DECODER | | | +--+--+ | | | | |CRSR +------------+-------------+ +-------------------+ | |LEFT | K2 PIN-22 | | | +-----+ +-----------+ | | +-----+ +-----+ / | | NMI | <---------+RESTR+----+ +-------------------------------------------------+ |PIN-3| | | | +-----+ +-----+ | | | +-----+ +-----+ / (LOCKING) | | R8 | <---------+CAPS +----+ +-------------------------------------------------+ |PIN-2| |LOCK | +-----+ +-----+ Keyboard Notes: 1/ The 64 keys under C0 through C7 occupy the same matrix position as in the C/64, as does the RESTORE key. Including SHIFT-LOCK, there are 66 such keys. 2/ The extended keyboard consists of the 8 keys under the C8 output. Counting the CAPS-LOCK key, there are 9 new keys. The C/64 does not scan these keys. 3/ The new CURSOR LEFT and CURSOR UP keys simulate a CURSOR plus RIGHT SHIFT key combination. 4/ The keyboard mechanism will be mechanically similar to that of the C128. 2.2. Form Factor EXPANSION SERIAL USER PORT STEREO RGBA RF COMPOSITE FAST DISK PORT BUS (PARALLEL) L R VIDEO VIDEO VIDEO PORT ######### #### ######### # # ##### ### ##### #### |~ ~~~ ~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~ ~~~~~ ~~| # | # POWER CONNECTOR | | +------------------+ ## POWER SWITCH | | | | | # | | # CONTROL PORT #2 | | # | 3.5" | | +--------------------------+ | | # | | | DISK DRIVE | # CONTROL PORT #1 | | | | # | RAM EXPANSION (BOTTOM) | | | | | | | | ## RESET | | | EJECT | | +--------------------------+ +------------+---+-+ | +---+ | | | +---------------------------------------------------------------------------+ NOTES: 1. Dimensions: about 18" wide, 8" deep, 2" high. 2. Disk unit faces forward. 2.3. The CSG 4510 Microcontroller Chip 2.3.1. Description This specification describes the requirements for a single chip 8-bit microcontroller unit fabricated in 2U CMOS double-metal technology for high speed and low power consumption. The IC is a fully static device that contains an enhanced 6502 microprocessor (65CE02), four independent 16-bit interval timers/two 24-hour (AM/PM) time of day clocks each with programmable alarm, full-duplex serial I/O (UART) channel with programmable baud rate generator, built-in memory map function to access up to 1 megabyte of memory, two 8-bit shift registers for synchronous serial I/O, and 30 individually programmable I/O lines. 2.3.2. Configuration This IC device shall be configured in a standard, 84-pin plastic chip carrier package. [*** Pinout below will change for 4510R5 ***] A A A F S C S C S V V C C R E R I N R T T 2 1 0 L R N P N P C S O A E X S R M X X E A Q T 1 T 2 C S L P S T T Q I D D S G I 1 2 8 S E R R * * T 2 N L T * * * * K * 1 1 8 8 8 8 8 7 7 7 7 7 1 0 9 8 7 6 5 4 3 2 1 4 3 2 1 0 9 8 7 6 5 A3 12 +---------------------------------------+ 74 C7MHZ A4 13 | | 73 SRQDAT A5 14 | | 72 SRQCLK A6 15 | | 71 SRQATN A7 16 | | 70 PA2 A8 17 | | 69 COL7 A9 18 | | 68 COL6 A10 19 | | 67 COL5 A11 20 | | 66 COL4 A12 21 | | 65 COL3 A13 22 | CSG 4510 | 64 COL2 A14 23 | | 63 COL1 A15 24 | | 62 COL0 A16 25 | | 61 ROW7 A17 26 | | 60 ROW6 A18 27 | | 59 ROW5 A19 28 | | 58 ROW4 PSYNC 29 | | 57 ROW3 AEC 30 | | 56 ROW2 DMA* 31 | | 55 ROW1 NOIO 32 +---------------------------------------+ 54 ROW0 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 N D D D D D D D D V P R P P P P P P P P P O B B B B B B B B C H / B B B B B B B B C M 7 6 5 4 3 2 1 0 C O W 0 1 2 3 4 5 6 7 2 A P 2.3.3. Functional Description 2.3.3.1. Pin Description PIN PIN SIGNAL NAME NUMBER DIRECTION DESCRIPTION ---- ------ --------- VSS 1 IN This is the power ground signal (0 volts). VCC 2,42 IN This is the power supply signal (+5 volts). SPB, 3 I/O The SPA and SPB signals are open-drain SPA 5 I/O and bidirectional, each with a 3Kohm (min.) passive pull-up. The SPA and SPB signals are the data lines used by the two 8-bit synchronous serial port registers. In input mode, SPA and SPB are clocked into the device on the rising edge of the CNTA and CNTB clocks, respectively. In the output mode, SPA and SPB change on the falling edge of the CNTA and CNTB clocks, respectively. CNTB, 4 I/O The CNTA and CNTB signals are open-drain CNTA 6 I/O and bidirectional, each with a 3K ohm (min.) passive pull-up. These pins are internally synchronized to the PH0 clock and then used to clock the synchronous serial registers, in input mode. In output mode, each pin will reflect the clock signal derived from the corresponding timer. FLAGA/ 1 I/O The FLAGA/ and FLAGB/ inputs are negative FLAGB/ 8 IN edge sensitive input signals. A passive pull-up (3Kohm min.) is tied on each of these pins. They are internally synchronized to the PH0 clock and are used as general purpose interrupt inputs. Any negative transition on either of these signals will cause the device to start an interrupt sequence, provided that the proper bit is set in each of the interrupt mask registers. The device-will drop the IRQ/ line to indicate that an interrupt sequence is underway. *** When the FAST SERIAL MODE is enabled the CNTA, SPA and *** *** FLAGA/ lines will not function as described above. See *** *** section 2.5.6. for FAST SERIAL MODE description. *** A0-A19 9 thru 28 I/O Address Bus - This is a 20 bit bi-directional bus with tri-state outputs. The output of each address line is TTL compatible, capable of driving two standard TTL loads and 55 pf. When the AEC or DMA/ line goes low, the bus goes tri-state. If AEC only is low, A17, A18 and A19 will each reflect the state of the A16 line. During an I/O access (IO/ is low), A0-A3, A8 and A9 are used to select an internal I/O register. If AEC is high, the bus will be driven by the CPU and A16-A19 will point to a mapped memory location (if MAP/ is low). If memory is not mapped (MAP/ is high), A16-A19 will be low. PSYNC 29 OUT This output line is provided to identify those cycles in which the microprocessor is doing an OP CODE fetch. The PSYNC line goes high during PHI of an OP CODE fetch and stays high for the remainder of that cycle. If AEC or DMA/ is low during the rising edge of PHI, in which pulse PSYNC went high, the processor will stop in its current state and will remain, in the state until either AEC or DMA/ goes high. In this manner, the SYNC signal can be used to control either the AEC or DMA/ line to cause single instruction execution. AEC 30 IN This input signal is the Address Enable Control line. When high, the address bus, R/W are valid. When low, the address bus, R/W and MAP/ are in a high-impedance state except for A17, A18 and A19 each of which will be connected to the A16 line. DMA/ 31 IN This signal is connected to a 3K passive pull- up. When this signal is low the address bus and R/W will be tri-stated. This will allow external DMA devices to assume control of the system bus lines. (READY) Internal Signal This signal is generated internally via the AEC and DMA/ lines. The READY signal goes high when both AEC and DMA/ are high. It goes low if either AEC or DMA/ goes low. The READY signal allows the user to single-cycle the microprocessor on all cycles including write cycles. A low state on either DMA/ or AEC during the rising transition of phase one (PHI) will deassert the READY line and halt the micro processor with the output address lines holding the current address. This feature allows microprocessor interfacing with low speed memory as well as fast (max 2 cycle) Direct Memory Access (DMA). IO/ 32 IN This input signal is used to select the internal registers of the device, provided memory is not being mapped by the CPU. MAP/ 33 OUT This signal is passively pulled-up (3 Kohm) whenever DMA/ or AEC is pulled low. This output signal is used to indicate whether or not memory is being mapped by the device. If the CPU is addressing a mapped memory region the MAP/ line will go low and will inhibit the IO/ line from selecting an internal register. If the CPU is not mapping memory the MAP/ line will be-high and A16-A19 will be kept low. DB7-DB0 34 thru 41 I/O D0-D7 form an 8 bit bi-directional data bus for data exchanges to and from the internal CPU (the 65CE02) and the device internal registers. It is also used to communicate with external peripheral devices. The output buffers are capable of driving two standard TTL loads and 55pf. R/W 43 I/O This signal is generated by the CPU to control the direction of data transfers on the data bus. This line is high except when the CPU is writing to memory, an internal I/O register or an external device. When the AEC or DMA/ signal is low, the R/W becomes tri-state. PH0 44 IN This clock is a TTL compatible input used for. internal device operation and as a timing reference for communicating with the system data bus. Two internal clocks are generated by the device; phase two (PH2) is in phase with PH0, and phase one (PH1) is 180 degrees out of phase with PH0. PC/ 53 OUT This output line is a strobe signal and is Centronics interface compatible. The signal goes low following a read or write access of PORT D. PRD0-PRD7 45 thru 52 I/O These are three 8-bit ports with each of their PRB0-PRB7 54 thru 61 I/O lines having a passive pull-up (min. 3K ohm) PRA0-PRA7 62 thru 69 I/O as well as active pull-up and pull-down transistors. Each individual port line may be programmed to be either input or output. PRC2 70 I/O This line corresponds to PORT C, bit 2. It has passive pull-up (min. 3k ohm) as well as active pull-up and pull-down transistors. The line can be configured as input or output. PRC2 becomes the external shift register clock when the UART is configured to operate in the synchronous mode, otherwise PRC2 operates as normal. PRC3 71 OUT This signal is an open drain output with a passive pull-up (1K ohm min). It corresponds to bit 3 of PORT C. When this port bit is set as an input, the PRC3 line is driven low; reading the port bit will give a high. If configured as an output, reading this port bit will not give the-status of the PRC3 line but the value previously written on the PORT C data reg. bit 3. PRC46 72 I/O This is an open drain bi-directional signal with a passive pull-up (1K ohm min). Bit 6 of PORT C is always configured as an input; the bit will give the status of the PRC46 line anytime the the port is read, regardless of what is written in the data direction register. If bit 4 of PORT C is set as an input, the PRC46 line will be pulled low; reading the port bit will give a high. If bit 4 is configured as an output, PRC46 will be pulled low if bit 4 in the port data register is high, otherwise the PRC46 line will float to a high. PRC57 73 I/O This is an open drain bi-directional signal with a passive pull-up (1K ohm min). Bit 7 of PORT C is always configured as an input; the bit will give the status of the PRC57 line anytime the the port is read, regardless of what is written in the data direction register. If bit 5 of PORT C is set as an input, the PRC57 line will be pulled low; reading the port bit will give a high. If bit 5 is configured as an output, PRC57 will be pulled low if bit 5 in the port data register is high, otherwise the PRC57 line will float to a high. PRE0,PRE1 83, 84 I/O This a 2-bit port with each line having a passive pull-up (min. 3K ohm) as well as active pull-up and pull-down transistors. Each indi- vidual port line may be programmed to be eithi. input or output. BAUDCLK 74 IN This Input is a 7MHz clock used to drive the UART Baud Rate Generator, and is assumed to be synchronous with the PHO clock. This clock is also divided down to 1MHz to drive the interval timers, and down to 10Hz to drive the TOD timers. This clock is also used to time out the FOR and RESTORE (RSTR*) circuits. TEST 75 IN When this input goes to a high state, the device will operate in a test mode. The test mode will allow the BAUDCLK dividers to be initialized and the TOD and interval timers to be driven directly by the BAUDCLK clock, bypassing all the dividers. TXD 76 OUT This is the UART transmit data output line. The LSB of the Transmit Data Register is the first data bit transmitted. The data transmission rate (baud rate) is determined by the value written to the Baud Rate Timer latches. RXD 77 IN This is the UART receive data input line and is connected to a passive pull-up (1K ohm min) The first data bit received is loaded into the LSB of the Receive Data Register. The receiver data rate must be the same as that determined by the value written to the Baud Rate Timer latches. NMI/ 78 I/O The NMI/ pin is an open drain bi-directional signal. A passive pull-up (3K ohms minimum) is tied on this pin, allowing multiple NMI/ sources to be tied together. A negative transition on this pin requests a non-maskable interrupt sequence to be generated by the microprocessor. The interrupt sequence will begin with the first PSYNC after a multiple-cycle opcode. NMI/ inputs cannot be masked by the processor status register I flag. The two program counter bytes PCH and PCL, and the processor status register P, are pushed onto the stack. Then the program counter bytes PCL and PCH are loaded from memory addresses FFFA and FFFB/ respectively. NOTE: Since this interrupt is non-maskable, another NMI/ can occur before the first is finished. Care should be taken to avoid this. The NMI/ line is normally off (high impedance) and the device will activate it low as described in the functional description. AEC and DMA/ must be high for any interrupt to be recognized. IRQ/ 79 I/O The Interrupt Request line (IRQ/) is an open drain bi-directional signal. A passive pull- up (3K Ohms minimum) is tied on this pin/ allowing multiple IRQ/ sources to be connected together. This pin is sampled during PH2 and when a negative transition is detected an inter- rupt will be activated, only if the mask flag (I) in the status register is low. The inter- rupt sequence will begin with the first PSYNC after a multiple-cycle opcode. The two program counter bytes PCH and PCL, and the processor status register P, are stored-onto the stack; the interrupt mask flag is set high so that no. further IRQ/'s may occur. At the end of this cycle, the program counter low byte (PCL) will be loaded from address FFFE/ and the high byte (PCH) from FFFF, thus transferring program control to the vector located at this addresses. The IRQ/ line is normally off (high impedance) and the device will activate it low as described in the functional descriptioni AEC and DMA/ must be high for any interrupt to be recognized. RESTR/ 80 IN This input is tied to a 3K ohm (min.) passive pull-up. A bounce eliminator circuit is used on this pin to remove any bounce during its falling transition, if the pin is tied to a contact closure. If the device sees a negative transition on this pin, it will immediately assert the NMI/ line to start a Non-Maskable In- terrupt sequence. The device will ignore any subsequent transitions on the RESTR/ line until 4.2ms has elapsed, at which time the NMI/ line is deasserted. EXTRST/ 81 OUT This output is an open drain output with a min. 1K ohm pull-up. This pin will only go to a low state during power-up, and will stay low until .9 seconds after VDD has reached its operating voltage. RESET/ 82 I/O The Reset line (RESET/) is an open drain bi- directional signal. A passive pull-up (1K ohm minimum) is tied on this pin, allowing any ex- ternal source to initialize the device. A low on RESET/ will instantly initialize the internal 65CE02 and all internal registers. All port pins are set as inputs and port registers to zero (a read of the ports will return all highs because of passive pull-ups); all timer control registers are set to zero and all timer latches to ones. All other registers are reset to zero. During power-up RESET/ is held low and will go high .9 seconds after VDD reaches the operating voltage. If pulled low during operation, the currently executing opcode will be terminated. The B and 2 registers will be cleared. The stack pointer will be set to "byte" mode, with the stack page set to page 1. The processor status bits E and I will be set. When the high transition is detected/the reset sequence begins on the CPU cycle. The first four cycles of the reset sequence do nothing. Then the program counter bytes PCL and PCH are loaded from memory addresses FFFC and FFFD, and normal program execution begins. 2.3.3.2. 4510R3 Timing Description +---+ +---+ -----------| |-----------------------------| |---------AEC, DMA +---+ +---+ TAES---| + |--TAEH |----- TPWH -----| -------------+ +----------------+ | | | PH0 +----------------+ +----------- |----- TPWL -----| TAIS--| |-- --| |--TAIH -----------------+ +---------------------+ NOIO,R/W +----------+ VALID +-------- A0-A19/NOMAP -----------------+ +---------------------+ (INPUT) ---|TAOS |--- ---| |--TAOH ----------------+ +-----------------------------+ +---- PSYNC,R/W +---+ VALID +---+ A0-A19/NOMAP ----------------+ +-----------------------------+ +---- (OUTPUT) TDIS|- -+- -|TDIH |--TDOS--| |- -|TDOH +-------+ +-----------+ --------+ VALID +-----------------------+ VALID +------ D0-D7 +-------+ +-----------+ ------+ +--------- | | AEC, DMA +---------------+ --| |--TAZ --| |--TZA --------+ +------- ON +---------------+ ON D0-D7,R/W/A0-A15(AEC, DMA) --------+ +-------A16-A19 (DMA) |--- TCH ---| -------+ +-----------+ | | | C7MHZ +---------+ +------ |---TCL---| --| |--TCCL ---------------------------+ | PH0 +-------- Param Description MIN TYP MAX ----- ------------------------- --- --- --- Tpwh PH0 clock high time 65 135 - Tpwl PH0 clock low time 65 135 - Taes AEC, DMA setup to PH0 falling 30 - - Taeh AEC, DMA hold from PH0 falling 10 - - Tais address input setup to PH0 rising 20 - - Tain address input hold from PH0 falling 10 - - Taos address output setup from PH0 falling - - 50 Taoh address output hold from PH0 falling 15 - - Tdis data input setup to PH0 falling 40 - - Tdih data input hold from PH0 falling 10 - - Tdos data output setup from PH0 rising - - 50 Tdoh data output hold from PH0 falling 30 - - Taz address off from AEC or DMA falling 0 15 20 Tza address on from AEC and DMA rising 15 - 30 Tch C7MHZ clock high time 65 - - Tcl C7MHZ clock low time 65 - - TccL C7MHZ delay from PH0 0 - 50 2.3.3.3. Register Description This device contains a total of 41 I/O peripheral registers which can be accessed after the following conditions are met. In a an access cyclethe device must be in a non-mapped mode (MAP/ line is not asserted), the IO/ line must be in an active low state and the AO-A3, A8 and A9 address-lines must contain the valid address of the register to be accessed. In addition the state of the R/W line will indicate whether a read (R/W is "high") write (R/W is "low") cycle is under way. A9 A8...A3 A2 A1 A0 HEX ADD REG SYMBOL REGISTER NAME +--------------------+-------+-----------+---------------------------+ | 0 0 0 0 0 0 | 0X0 | PRA | Peripheral Data Reg A | | 0 0 0 0 0 1 | 0X1 | PRB | Peripheral Data Reg B | | 0 0 0 0 1 0 | 0X2 | DDRA | Data Direction Reg A | | 0 0 0 0 1 1 | 0X3 | DDRB | Data Direction Reg B | | 0 0 0 1 0 0 | 0X4 | TA LO | Timer A Low Register | | 0 0 0 1 0 1 | 0X5 | TA HI | Timer A High Register | | 0 0 0 1 1 0 | 0X6 | TB LO | Timer B Low Register | | 0 0 0 1 1 1 | 0X7 | TB HI | Timer B High Register | | 0 0 1 0 0 0 | 0X8 | TODATS | TODA 10ths Sec Register | | 0 0 1 0 0 1 | 0X9 | TODAS | TODA Seconds Register | | 0 0 1 0 1 0 | 0XA | TODAM | TODA Minutes Register | | 0 0 1 0 1 1 | 0XB | TODAH | TODA Hours-AM/PM Reg. | | 0 0 1 1 0 0 | 0XC | SDRA | SERIALA Data Register | | 0 0 1 1 0 1 | 0XD | ICRA | INTERRUPTA Control Reg. | | 0 0 1 1 1 0 | 0XE | CRA | Control Register A | | 0 0 1 1 1 1 | 0XF | CRB | Control Register B | | 0 1 0 0 0 0 | 1X0 | PRC | Peripheral Data Reg. C | | 0 1 0 0 0 1 | 1X1 | PRD | Peripheral Data Reg. D | | 0 1 0 0 1 0 | 1X2 | DDRC | Data Direction Reg C | | 0 1 0 0 1 1 | 1X3 | DDRD | Data Direction Reg D | | 0 1 0 1 0 0 | 1X4 | TC LO | Timer C Low Register | | 0 1 0 1 0 1 | 1X5 | TC HI | Timer C High Register | | 0 1 0 1 1 0 | 1X6 | TD LO | Timer D Low Register | | 0 1 0 1 1 1 | 1X7 | TD HI | Timer D High Register | | 0 1 1 0 0 0 | 1X8 | TODBTS | TODB 10ths of Sec Reg. | | 0 1 1 0 0 1 | 1X9 | TODBS | TODB Seconds Register | | 0 1 1 0 1 0 | 1XA | TODBM | TODB Minutes Register | | 0 1 1 0 1 1 | 1XB | TODBH | TODB Hours-AM/PM Reg. | | 0 1 1 1 0 0 | 1XC | SDRB | SERIALB Data Register | | 0 1 1 1 0 1 | 1XD | ICRB | INTERRUPTB Control Reg. | | 0 1 1 1 1 0 | 1XE | CRC | Control Register C | | 0 1 1 1 1 1 | 1XF | CRD | Control Register D | | 1 0 0 0 0 0 | 2X0 | DREG | Receive/Transmit Data Reg| | 1 0 0 0 0 1 | 2X1 | URSR | UART Status Register | | 1 0 0 0 1 0 | 2X2 | URCR | UART Control Register | | 1 0 0 0 1 1 | 2X3 | BRLO | Baud Rate Timer LO Reg. | | 1 0 0 1 0 0 | 2X4 | BRHI | Baud Rate Timer HI Reg. | | 1 0 0 1 0 1 | 2X5 | URIEN | UART IRQ/NMI Enable Reg. | | 1 0 0 1 1 0 | 2X6 | URIFG | UART IRQ/NMI Flag Reg. | | 1 0 0 1 1 1 | 2X7 | PRE | Peripheral Data Reg. E | | 1 0 1 0 0 0 | 2X8 | DDRE | Data Direction E | | 1 0 1 0 0 1 | 2X9 | FSERIAL | Fast Serial Bus Control | +--------------------+-------+-----------+---------------------------+ REGISTER ADDRESS ALLOCATION TABLE 1 The functional description of the memory mapper follows in section 2.3.4. The Fast Serial register is described in section 2.3.5.6. 2.3.3.3.1. REGISTER BIT ALLOCATION R/W REG NAME D7 D6 D5 D4 D3 D2 D1 D0 +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |0X0| PRA | PA7 | PA6 | PA5 | PA4 | PA3 | PA2 | PA1 | PA0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |0X1| PRB | PB7 | PB6 | PB5 | PB4 | PB3 | PB2 | PB1 | PB0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |0X2| DDRA | DPA7 | DPA6 | DPA5 | DPA4 | DPA3 | DPA2 | DPA1 | DPA0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |0X3| DDRB | DPB7 | DPB6 | DPB5 | DPB4 | DPB3 | DPB2 | DPB1 | DPB0 | +-----+---+------+---+------+------+------+------+------+------+------+------+ | READ|0X4| TA LO| | TAL7 | TAL6 | TAL5 | TAL4 | TAL3 | TAL2 | TAL1 | TAL0 | +-----+---+------+ T +------+------+------+------+------+------+------+------+ | READ|0X5| TA HI| I | TAH7 | TAH6 | TAH5 | TAH4 | TAH3 | TAH2 | TAH1 | TAH0 | +-----+---+------| M +------+------+------+------+------+------+------+------+ | READ|0X6| TB LO| E | TBL7 | TBL6 | TBL5 | TBL4 | TBL3 | TBL2 | TBL1 | TBL0 | +-----+---+------| R +------+------+------+------+------+------+------+------+ | READ|0X7| TB HI| | TBH7 | TBH6 | TBH5 | TBH4 | TBH3 | TBH2 | TBH1 | TBH0 | +-----+---+------+---+------+------+------+------+------+------+------+------+ | | | | P | | | | | | | | | |WRITE|0X4| TA LO| R | PAL7 | PAL6 | PAL5 | PAL4 | PAL3 | PAL2 | PALI | PAL0 | +-----+---+------+ E +------+------+------+------+------+------+------+------+ |WRITE|0X5| TA HI| S | PAH7 | PAH6 | PAH5 | PAH4 | PAH3 | PAH2 | PAH1 | PAHO | +-----+---+------+ C +------+------+------+------+------+------+------+------+ |WRITE|0X6| TB LO| A | PBL7 | PBL5 | PBL5 | PBL4 | P3L3 | PBL2 | PBL1 | PBL0 | +-----+---+------+ L +------+------+------+------+------+------+------+------+ |WRITE|0X7| TB HI| E | PBH7 | PBH6 | PBH5 | PBH4 | PBH3 | PBH2 | PBH1 | PBH0 | | | | | R | | | | | | | | | +-----+---+------+---+------+------+------+------+------+------+------+------+ | | | | T | | | | | | | | | | READ|0X8|TODATS| O | 0 | 0 | 0 | 0 | TA8 | TA4 | TA2 | TA1 | +-----+---+------+ D +------+------+------+------+------+------+------+------+ | READ|0X9|TODAS | |(*) 0 | SAH4 | SAH2 | SAH1 | SAL8 | SAL4 | SAL2 | SAL1 | +-----+---+------+ T +------+------+------+------+------+------+------+------+ | READ|0XA|TODAM | I |(*) 0 | MAH4 | MAH2 | MAH1 | MAL8 | MAL4 | MAL2 | MAL1 | +-----+---+------+ M +------+------+------+------+------+------+------+------+ | READ|0XB|TODAH | E | APM | 0 | 0 | HAH | HAL8 | HAL4 | HAL2 | HAL1 | +-----+---+------+ +------+------+------+------+------+------+------+------+ | | | | | (*) IN TEST MODE: WILL READ DIVIDER STAGE OUTPUTS | +-----+---+------+---+------+------+------+------+------+------+------+------+ | | | | T | | | | | | | | | |WRITE|0X8|TODATS| 0 | 0 | 0 | 0 | 0 | TA8 | TA4 | TA2 | TA1 | +-----+---+------+ +------+------+------+------+------+------+------+------+ |WRITE|0X9|TODAS | | 0 | SAH4 | SAH2 | SAH1 | SAL8 | SAL4 | SAL2 | SAL1 | +-----+---+------+ L +------+------+------+------+------+------+------+------+ |WRITE|0XA|TODAM | A | 0 | MAH4 | MAH2 | MAH1 | MAL8 | MAL4 | MAL2 | MAL1 | +-----+---+------+ T +------+------+------+------+------+------+------+------+ |WRITE|0XB|TODAH | C | APM | 0 | 0 | HAH | HAL8 | HAL4 | HAL2 | HAL1 | | | | | H | | | | | | | | | | | | | E | IF CRB ALARM BIT=1 , ALARM REGISTER IS WRITTEN | | | | | S | IF CRB ALARM BIT=0 , TOD REGISTER IS WRITTEN | +-----+---+------+---+------+------+------+------+------+------+------+------+ | R/W |0XC| SDRA | SRA7 | SRA6 | SRA5 | SRA4 | SRA3 | SRA2 | SRA1 | SRA0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | READ|0XD| ICRA | IRA | 0 | 0 | FLGA | SPA | ALRMA| TB | TA | | | |(INT DATA)| | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ |WRITE|0XD| ICRA |AS/C~ | -- | -- | FLGA | SPA | ALRMA| TB | TA | | | |(INT MASK)| | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |0XE| CRA | TODA | SPA | TMRA | LOADA| RUN-A| OUT-A| PRB6 |STARTA| | | | | IN | MODE |INMODE| | MODE | MODE | ON | | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |0XF| CRB |ALARM |TIMERB|INMODE| LOADB| RUN-B| OUT-B| PRB7 |STARTB| | | | |(TODA)| CRB6 | CRB5 | | MODE | MODE | ON | | +-----+---+----------+------+------+------+------+------+------+------+------+ | READ|1X0| PRC | PC7 | PC6 | PC5 | PC4 | PC3 | PC2 | PC1 | PC0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |1X1| PRD | PD7 | PD6 | PD5 | PD4 | PD3 | PD2 | PD1 | PD0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |1X2| DDRC | DPC7 | DPC6 | DPC5 | DPC4 | DPC3 | DPC2 | DPC1 | DPC0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |1X3| DDRD | DPD7 | DPD6 | DPD5 | DPD4 | DPD3 | DPD2 | DPD1 | DPD0 | +-----+---+------+---+------+------+------+------+------+------+------+------+ | READ|1X4| TC LO| | TCL7 | TCL6 | TCL5 | TCL4 | TCL3 | TCL2 | TCL1 | TCL0 | +-----+---+------+ T +------+------+------+------+------+------+------+------+ | READ|1X5| TC HI| I | TCH7 | TCH6 | TCH5 | TCH4 | TCH3 | TCH2 | TCH1 | TCH0 | +-----+---+------| M +------+------+------+------+------+------+------+------+ | READ|1X6| TD LO| E | TDL7 | TDL6 | TDL5 | TDL4 | TDL3 | TDL2 | TDL1 | TDL0 | +-----+---+------| R +------+------+------+------+------+------+------+------+ | READ|1X7| TD HI| | TDH7 | TDH6 | TDH5 | TDH4 | TDH3 | TDH2 | TDH1 | TDH0 | +-----+---+------+---+------+------+------+------+------+------+------+------+ | | | | P | | | | | | | | | |WRITE|1X4| TC LO| R | PCL7 | PCL6 | PCL5 | PCL4 | PCL3 | PCL2 | PCL1 | PCL0 | +-----+---+------+ E +------+------+------+------+------+------+------+------+ |WRITE|1X5| TC HI| S | PCH7 | PCH6 | PCH5 | PCH4 | PCH3 | PCH2 | PCH1 | PCH0 | +-----+---+------+ C +------+------+------+------+------+------+------+------+ |WRITE|1X6| TD LO| A | PDL7 | PDL6 | PDL5 | PDL4 | PDL3 | PDL2 | PDL1 | PDL0 | +-----+---+------+ L +------+------+------+------+------+------+------+------+ |WRITE|1X7| TD HI| E | PDH7 | PDH6 | PDH5 | PDH4 | PDH3 | PDH2 | PDH1 | PDH0 | | | | | R | | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ | | | | T | | | | | | | | | |READ |1X8|TODBTS| O | 0 | 0 | 0 | 0 | TB8 | TB4 | TB2 | TB1 | +-----+---+------+ D +------+------+------+------+------+------+------+------+ |READ |1X9|TODBS | |(*) 0 | SBH4 | SBH2 | SBH1 | SBL8 | SBL4 | SBL2 | SBL1 | +-----+---+------+ T +------+------+------+------+------+------+------+------+ |READ |1XA|TODBM | I | 0 | MBH4 | MBH2 | MBH1 | MBL8 | MBL4 | MBL2 | MBL1 | +-----+---+------+ M +------+------+------+------+------+------+------+------+ |READ |1XB|TODBH | E | BPM | 0 | 0 | HBH | HBL8 | HBL4 | HBL2 | HBL1 | | | | | R | | | | | | | | | | | | | | (*) IN TEST MODE: WILL READ DIVIDER STAGE OUTPUT | +-----+---+------+---+------+------+------+------+------+------+------+------+ |WRITE|1X8|TODBTS| T | 0 | 0 | 0 | 0 | TB8 | TB4 | TB2 | TB1 | +-----+---+------+ O +------+------+------+------+------+------+------+------+ |WRITE|1X9|TODBS | D | 0 | SBH4 | SBH2 | SBH1 | SBL8 | SBL4 | SBL2 | SBL1 | +-----+---+------+ L +------+------+------+------+------+------+------+------+ |WRITE|1XA|TODBM | A | 0 | MBH4 | MBH2 | MBH1 | MBL8 | MBL4 | MBL2 | MBL1 | +-----+---+------+ T +------+------+------+------+------+------+------+------+ |WRITE|1XB|TODBH | C | BPM | 0 | 0 | HBH | HBL8 | HBL4 | HBL2 | HBL1 | | | | | H | | | | | | | | | | | | | E | IF CRD ALARM BIT=1 , ALARM REGISTER IS WRITTEN | | | | | S | IF CRD ALARM BIT=0 , TOD REGISTER IS WRITTEN | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |1XC| SDRB | SRB7 | SRB6 | SRB5 | SRB4 | SRB3 | SRB2 | SRB1 | SRB0 | +-----+---+----------+------+------+------+------+------+------+------+------+ |READ |1XD| ICRB | IRB | 0 | 0 | FLGB | SPB | ALRMB| TD | TC | | | |(INT DATA)| | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ |WRITE|1XD| ICRB |BS/C~ | -- | -- | FLGB | SPB | ALRMB| TD | TC | | | |(INT MASK)| | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |1XE| CRC | TODB | SPB | TMRC | LOADC| RUN-C| OUT-C| PRD6 |STARTC| | | | | IN | MODE |INMODE| | MODE | MODE | ON | | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |1XF| CRD |ALARM |TIMERD|INMODE| LOADD| RUN-D| OUT-D| PRD7 |STARTD| | | | |(TODB)| CRD6 | CRD5 | | MODE | MODE | ON | | +-----+---+----------+------+------+------+------+------+------+------+------+ | READ|2X0| DREG | RCV7 | RCV6 | RCV5 | RCV4 | RCV3 | RCV2 | RCV1 | RCV0 | |(RECEIVE DATA REG) | | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ |WRITE|2X0| DREG | XMT7 | XMT6 | XMT5 | XMT4 | XMT3 | XMT2 | XMT1 | XMT0 | |(TRANSMIT DATA REG) | | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ | READ|2X1| URSR |TDONE | EMPTY| ENDT | IDLE | FRME | PRTY | OVR | FULL | +-----+---+----------+------+------+------+------+------+------+------+------+ |WRITE|2X1| URSR | -- | -- | ENDT | IDLE | -- | -- | -- | -- | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |2X2| URCR | XMITR| RCVER| UART | MODE | CHAR LENGTH |PARITY PARITY| | | | | EN | EN | UM1 | UM0 | CH1 CH0 | EN | EVEN | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |2X3| BRL0 | BRL7 | BRL6 | BRL5 | BRL4 | BRL3 | BRL2 | BRL1 | BRL0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |2X4| BRHI | BRH7 | BRH6 | BRH5 | BRH4 | BRH3 | BRH2 | BRH1 | BRH0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |2X5| URIEN | XDIRQ| RDIRQ| XDNMI| RDNMI| -- | -- | -- | -- | +-----+---+----------+------+------+------+------+------+------+------+------+ | READ|2X6| URIFG | XDIRQ| RDIRQ| XDNMI| RDNMI| -- | -- | -- | -- | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |2X7| PRE | -- | -- | -- | -- | -- | -- | PE1 | PE0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |2X8| DDRE | -- | -- | -- | -- | -- | -- | DPE1 | DPE0 | +-----+---+----------+------+------+------+------+------+------+------+------+ | R/W |2X9| FSERIAL |*DMODE|*FSDIR| -- | -- | -- | -- | -- | -- | +-----+---+----------+------+------+------+------+------+------+------+------+ REGISTER BIT ALLOCATION TABLE 2 2.3.4. Memory Mapper The microprocessor core is actually a C4502R1 with some addittional instructions, used to operate the memory mapper. The former AUG (augment) opcode has been changed to MAP (mapper), and the former NOP (no-operation) has been changed to EOM (end-of- mapping-sequence). The 4510 memory mapper allows the microprocessor to access up to 1 megabyte of memory. Here's how. The 6502 microprocessor can only access 64K bytes of memory because it only uses addresses of 16 bit's. The 4502 is not different, nor is the 4510. But the 4510 memory mapper allows these addresses to be redirected to new physical addresses to access different parts of a much larger memory, within the 64K byte confinement window. The 64K window has been divided into eight blocks, and two regions, with four blocks in each region. Blocks 0 through 3 are in the "lower" region, and blocks 4 through 7 are in the "upper" region, as shown... +- +-----------+FFFF | | BLK 7 | | +-----------+E000 | | BLK 6 | UPPER REGION -+ +-----------+C000 | | BLK 5 | | +-----------+A000 | | BLK 4 | +- +-----------+8000 | | BLK 3 | | +-----------+6000 | | BLK 2 | LOWER REGION -+ +-----------+4000 | | BLK 1 | | +-----------+2000 | | BLK 0 | +- +-----------+ Each block can be programmed to be "mapped", or "non-mapped" via bits in the mapper's "mask" registers. NON-MAPPED means, simply, address out equals address in. Therefore, there are still only 64K bytes of non-mapped memory. MAPPED means that address out equals address in plus some offset. The offset is programmed via the mapper's "offset" registers. There are two "offset" registers. One is for the lower region, and one is for the upper region. The low-order 6 addresses are never mapped. The offsets are only added to the 12 high-order addresses. This means the smallest unit you can map to is 256 bytes, or one page. The 4510 has an output (NOMAP) which lets the outside world know when the processor is accessing mapped (0) or non-mapped (1) address. This is useful for systems where you may want I/O devices to be at fixed (non-mapped) addresses, and only memory at mapped addresses. It is possible, and likely, to have mapped, and unmapped memory at the same physical address. And, with offset registers set to zero, mapped addresses will match unmapped ones. The only difference is the NOMAP signal to tell whether the address is mapped or unmapped. To program the mapper, the operating system must load the A, X, Y, and Z registers with the following information, and execute a MAP opcode. Mapper Register Data 7 6 5 4 3 2 1 0 BIT +-------+-------+-------+-------+-------+-------+-------+-------+ | LOWER | LOWER | LOWER | LOWER | LOWER | LOWER | LOWER | LOWER | A | OFF15 | OFF14 | OFF13 | OFF12 | OFF11 | OFF10 | OFF9 | OFF8 | +-------+-------+-------+-------+-------+-------+-------+-------+ | MAP | MAP | MAP | MAP | LOWER | LOWER | LOWER | LOWER | X | BLK3 | BLK2 | BLK1 | BLK0 | OFF19 | OFF18 | OFF17 | OFF16 | +-------+-------+-------+-------+-------+-------+-------+-------+ | UPPER | UPPER | UPPER | UPPER | UPPER | UPPER | UPPER | UPPER | Y | OFF15 | OFF14 | OFF13 | OFF12 | OFF11 | OFF10 | OFF9 | OFF8 | +-------+-------+-------+-------+-------+-------+-------+-------+ | MAP | MAP | MAP | MAP | UPPER | UPPER | UPPER | UPPER | Z | BLK7 | BLK6 | BLK5 | BLK4 | OFF19 | OFF18 | OFF17 | OFF16 | +-------+-------+-------+-------+-------+-------+-------+-------+ After executing the MAP opcode, all interrupts are inhibited. This is done to allow the operating system is complete a mapping sequence without fear of getting an interrupt. An interrupt occurring before the proper stack-pointer is set will cause return address data to be written to an undesired area. Upon completing the mapping sequence, the operating system must remove the interrupt inhibit by executing a EOM (formerly NOP) opcode. Note that application software may execute NOPs with no effect. 2.3.5. Peripheral Control Functions 2.3.5.1. I/O Ports Ports A, B and D each consist of an 8-bit Peripheral Data Register (PR) and an 8-bit Data Direction Register (DDR). Port E consists of a 2-bit PR and DDR registers. If a bit in the DDR is set to one, the corresponding bit in the PR is an output, if a DDR bit is set to a zero, the corresponding PR bit is defined as an input. On a READ, the PR bit reflects the information present on the actual port pins (PRA0-PRA7, PRB0-PRB7, PRC2, PRD0-PRD7, PRE0-PRE1) for both input and output bits. All ports have passive pull-up devices as well as active pull-ups, providing both CMOS and TTL compatibility. In addition to normal I/O operation, PRB6, PRB7, PRD6 and PRD7 also provide timer output functions (refer to Control Register section, 2.5.8.). Only bit PC2 and DPC2 of PORT C meet the above description. The other bits function as described in the following. PC0,PC1 These signals are simply a register bits. When read, they will reflect the value previously written to the PRC register. PC4 This bit is a "high" if it's configured as input (DPC4 is a "low"). If configured as output (DPC4 is a "high"), the bit will reflect its previous written value when PORT C is read. Then the PRC46 pin is pulled "low" if PC4 is "high"; otherwise, PRC46 is pulled-up through passive resistor. PC5 This bit is a "high" if it's configured as input (DPC5 is a "low"). If configured as output (DPC5 is a "high"), the bit will reflect its previous written value when PORT C is read. Then the PRC57 pin is pulled "low" if PC5 is "high"; otherwise, PRC57 is pulled-up through passive resistor. PC6,PC7 These bits are always configured as inputs. When PORT C (PRC) is read, PC6 and PC7 will reflect the values on the PRC46 and PRC57 pins, respectively. 2.3.5.2. Handshaking Handshaking on data transfers can be accomplished using the PC/ output pin and either the FLAGA/ or FLAGB/ input pin. The PC/ line will go low and stay low for two cycles, two cycles after a read or write to PORT D. This is required to meet Centronics Parallel Interface specs. The PC/ line can be used to indicate "data ready" at PORT D or "data accepted" from PORT D. Handshaking on 16-bit data transfers (using either PORT A or B and then PORT D) is possible by always reading or writing PORT A or PORT B first. The FLAG/ lines are negative edge sensitive inputs which can be used for receiving the PC/ output from other 4510 devices, or as general purpose interrupt inputs. A negative transition on FLAGA/ or FLAGB/ will set the FLAGA or FLAGB interrupt bits, respectively. 2.3.5.3. Interval Timers (Timer A, Timer B, Timer C, Timer D) Each interval timer consists of a 16-bit read-only Timer Counter and a 16-bit write-only Timer Latch (prescaler). Data written to the timer are latched in the Timer Latch, while data read from the timer are the present contents of the Timer Counter. The timers can be used independently or linked in pairs for extended operations (TIMER A may be linked with Timer B; TIMER C may be linked with TIMER D). The various timer modes allow generation of long time delays, variable width pulses, pulse trains and variable frequency waveforms. Utilizing the CNT inputs, the timers can count external pulses or measure frequency, pulse witdth and delay times of external signals. Each timer has an associated control register, providing independent control of the following functions (see bits functional description in section 2.5.8 below): Start/Stop Each timer may be started or stopped by the microprocessor at any time by writing to the START/STOP bit of the corresponding control register (CRA, CRB, CRB or CRC). PRB, PRD On/Off Control bits allow any of the timer outputs to appear on a PORT B or PORT D output line (PRB6 for TIMER A, PRB7 for TIMER B, PRD6 for TIMER C and PRD7 for TIMER D). Note that this function overrides the DDRB control bit and forces the appropriate PB or PC line to be an output. Toggle/Pulse Control bits select the ouputs applied to PORT B and PORT D. On every timer underflow the ouput can either toggle or generate a single positive pulse of one cycle duration. The Toggle output is set high whenever the appreciate timer is started and is set low by RESET/. One-Shot/Continuous Control bits select-either timer mode. In one-shot mode, the timer will count down from the latched value to zero, generate an interrupt, reload the latched value, then stop. In continuous mode, the timer will count from the latched value to zero, generate an interrupt, reload the latched value and repeat the procedure continuously. Force Load A strobe bit allows the timer latch to be loaded into the timer counter at any time, whether the timer is running or not. Input Mode Control bits allow selection of the clock used to decrement the timer. TIMER A or TIMER C can count C1MHZ clock pulses or external pulses applied to the CNTA or CNTB, respectively. The C1MHZ clock is obtained after internally dividing the C7MHZ by a factor of seven. TIMER B can count C1MHZ clock pulses, external pulses applied to the CNTA input, TIMER A underflow pulses or TIMER A underflow pulses while the CNTA pin is held high. TIMER D can count C1MHZ clock pulses, external pulses applied to the CNTB input, TIMER C underflow pulses or TIMER C underflow pulses while the CNTB pin is held high. The timer latch is loaded into the timer on any timer underflow, on a force load or following a write to the high byte of the prescaler while the timer is stopped. If the timer is running, a write to the high byte will load the timer latch, but not reload the counter. 2.3.5.4. Time of Day Clocks (TODA, TODB) The TODA and TODB clocks are special purpose timers for real-time applications. Each clock, TODA or TODB, consists of a 24-hour (AM/PM) clock with 1/10th second resolution. Each is organized into four registers: 10ths of seconds (TODATS, TODBTS), Seconds (TODAS, TODBS)/Minutes (TODAM, TODBM) and Hours (TODAH, TODBH). The AM/PM flag is in the MSB of the Hours register for easy testing. Each register reads out in BCD format to simplify conversion for driving displays, etc. Each TOD requires a 10HZ clock input to keep accurate timing. This 10HZ clock is generated by dividing the C7MHz clock input by a factor of 102273 for NTSC (60Hz) applications, or a factor of 101339 for PAL (50Hz) applications. The divider ratio is selected by the TODA IN and the TODB IN bits of the Control Registers, CRA and CRC, respectively (see 2.5.8). In addition to time-keeping, a programmable ALARM is provided for generating an interrupt at the desired time, from either of the TOD clocks. The ALARM registers registers are located at the same addresses as the corresponding TODA and TODB registers. Access to the ALARM is governed by bit 7 in the Control Registers CRB and CRD. The ALARM registers are write-only; any read of a TOD address will read time regardless of the state of the ALARM access control bits. A specific sequence of events must be followed for proper setting and reading of each TOD. A TOD is automatically stopped whenever a write to the corresponding Hours register occurs. The TOD will not start again until after a write to the proper 10ths of seconds register. This assures that a TOD will always start at the desired time. Since a carry from one stage to the next can occur at any time with respect to a read operation, a latching function is included to keep all Time of Day information constant during a read sequence. All four registers of each TOD latch on a read of the corresponding Hours register and remain latched until after a read of the corresponding 10ths of second register. A TOD continues to count when the output registers are latched. If only one register is to be read, there is no carry problem and the register can be read "on the fly", provided that any read of the Hours register if followed by a read of the proper 10ths of seconds, to disable the latching. 2.3.5.5. Serial Ports (SDRA, SDRB) Each serial port is a buffered, 8-bit synchronous shift register system. A control bit (CRA SPA bit, CRC SPB bit) selects input or output mode for either the SDRA or SDRB port. In input mode, data on the SPA or SPB pin is shifted into the corresponding shift register on the rising edge of the signal applied to the CNTA or CNTB pin, respectively. After 8 CNTA pulses, the data in the shift register is dumped into the SERIALA Data Register (SDRA) and an interrupt is generated, SPA bit is set in register ICRA. After 8 CNTB pulses, the data in the shift register is dumped into the SERIALB Data Register (SDRB) and an interrupt is generated, SPB bit is set in register ICRB. In the output mode, TIMER A is used for the baud rate generator of serial port A, Timer C for serial port B. Data is shifted on an SP pin at half the underflow rate of the TIMER used. The maximum baud rate possible is C1MHz divided by four, but the maximum useable baud rate will be determined by line loading and the speed at which the receiver responds to input data. Transmission will start following a write to Serial Data Register (provided the proper TIMER used is running and in continuous mode). The clock signal derived from TIMER A would appear as an output on the CNTA pin; the one from TIMER C would appear on the CNTB pin. The data in the Serial Data Register will be loaded into its corresponding shift register then shift out to the SPA or SPB pin when a CNTA or CNTB pulse occurs, respectively. Data shifted out becomes valid on the falling edge of its CNT clock and remains valid until the next falling edge. After 8 CNT pulses, an interrupt is generated to indicate more data can be sent. If the Serial Data Register was loaded with new information prior to this interrupt, the new data will automatically be loaded into the shift register and transmission will continue. If the microprocessor stays one byte ahead of the shift register, transmission will be continuous. If no further data is to be transmitted, after the 8th CNT pulse, CNT will return high and SP will remain at the level of the last data bit transmitted. SDR data is shifted out MSB first and serial input data should also appear on this format. The bidirectional capability of each of the Serial Ports and CNT clocks allows many 4510 to be connected to a common serial communication bus on which one Serial Port would act as a master, sourcing data and shift clock, while the other Serial Port (and all other ports from other 4510 devices) would act as slaves. All the CNT and SP outputs are open drain to allow such a common bus. Protocol for master/slave selection can be transmitted over the serial bus, or via dedicated handshaking lines. 2.3.5.6. FAST SERIAL MODE The FAST SERIAL logic consists of a 2-bit write-only register, which resides in location 0001 (hex). This register may only be accessed by the CPU if neither the AEC or DMA/ line is low. Upon reset, both bits in the register are forced low which allows the device to operate as normal (the CNTA, SPA, PRC57 and FLAGA/ lines will not be affected). Bit 1 of the FAST SERIAL register is the Fast Serial Mode disable bit (DMODE* bit). Bit 6 of the FAST SERIAL register is the FSDIR* bit. When the DMODE* bit is set high, the FSDIR* bit will be used as an output to control the fast serial data direction buffer hardware, and as an input to sense a fast disk enable signal. This function will affect the CNTA, SPA, PRC57 and FLAGA/ lines as summarized in the following table. DMODE* FSDIR* FUNCTION 0 0 Fast Serial mode is disabled. x 1 Both the FLAGA/ and the PRC57 lines will behave as outputs. The FLAGA/ output will reflect the state of the CNTA pin, whereas the PRC57 output will reflect the state of the SPA pin. 1 0 Both the CNTA and SPA lines will behave as outputs. The CNTA output will reflect the state of the FLAGA/ pin, whereas the SPA output will reflect that of the PRC57 pin. 2.3.5.7. Interrupt Control Registers (ICRA, ICRB) These registers control the following sources of interrupts: i. Underflows from TIMER A, TIMER B, TIMER C and TIMER D. ii. TODA ALARM and TODB ALARM. iii. SERIALA and SERIALB Port full/empty conditions. iv. FLAGA/ and FLAGB/ low transitions. The ICRA and ICRB registers each provides masking and interrupt information. ICRA and ICRB each consists of a write-only MASK register and a read-only-DATA register. Any interrupt will set the corresponding bit in the DATA register. Any interrupt which is enabled by the MASK register will set the IR bit (MSB) of its corresponding DATA register and bring the IRQ/ pin low. In a multi-chip system, the IR bit (IRA of ICRA or IRB of ICRB) can be polled to detect which chip has generated an interrupt request. The interrupt DATA register is cleared and the IRQ/ line returns high following a read of the DATA register. Since each interrupt sets and interrupt bit regardless of the MASK, and each interrupt bit can be selectively masked to prevent the generation of a processor interrupt, it is possible to intermix polled interrupts with true interrupts. However, polling either of the IR bits will cause its corresponding DATA register to clear, therefore, it is up to the user to preserve the information contained in the DATA registers if any polled interrupts were present. Both MASK (ICRA, ICRB) registers provide convenient control of individual mask bits. When writing to a MASK register, if bit 7 of the data written (corresponding to AS/C in ICRA, or BS/C in ICRB) is a ZERO, any mask bit written with a one will be cleared, while those bits written with a zero will be unaffected. In order for an interrupt flag to set the IR bit and generate an Interrupt Request, the corresponding MASK bit must be set in the corresponding MASK Register. 2.3.5.8. Control Registers (CRA, CRB, CRC, CRD) CRA (0XE): BIT Bit Name Function 0 STARTA 1=START TIMER A, 0=STOP TIMER A. This bit is automatically reset when TIMER A underflow occurs during one-shot mode. 1 PRB6 ON 1=TIMER A output appears on PRB6, 0=PRB6 normal port operation. 2 OUT-A MODE 1=TOGGLE output applied on port PRB6, 0=PULSE output applied on port PRB6. 3 RUN-A MODE 1=ONE-SHOT TIMER A operation, 0=CONTINUOUS TIMER A operation. 4 LOADA 1=FORCE LOAD on TIMER A (this is a STROBE input, there is no data storage, bit 4 will always read back a zero and writing a zero has no effect). 5 TMRA INMODE 1=TIMER A counts positive CNTA transitions, 0=TIMER A counts internal C1MHZ pulses. 6 SPA MODE 1=SERIAL A PORT output mode (CNTA sources shift clock), 0=SERIAL A PORT input mode (external shift clock on CNTA). 7 TODA IN 1=50 Hz operation. C7MHZ divided down by 101339 to generate TODA input of 10 Hz. 0=60 Hz operation. C7MHZ divided down by 102273 to generate TODA input of 10 Hz. CRB (0XF): BIT Bit Name Function (Bits 0-4 of the CRB register operate identically to bits 0-4 of the CR7 register, except that functions now apply to TIMER B and bit 1 control the output of TIMER B on PRB7). 5,6 TIMERB Bits 5 and 6 select one of four input modes for INMODE TIMER B as follows: CRB6 CRB5 0 0 TIMER B counts C1MHz pulses. 0 1 TIMER B counts positive CNTA transitions. 1 0 TIMER B counts TIMERA underflow pulses. 1 1 TIMER B counts TIMERA underflows while CNTA is high. 7 ALARM TODA 1=writing to TODA registers sets ALARM, 0=writing to TODA registers sets TODA clock. CRC (1XE): BIT Bit Name Function 0 STARTC 1=START TIMER C, 0=STOP TIMER C. This bit is automatically reset when TIMER C underflow occurs during one-shot mode. 1 PRD6 ON 1=TIMER C output appears on PRD6, 0=PRD6 normal port operation. 2 OUT-C MODE 1=TOGGLE output applied on port PRD6, 0=PULSE output applied on port PRD6. 3 RUN-C MODE 1=ONE-SHOT TIMER C operation, 0=CONTINUOUS TIMER C operation. 4 LOADC 1=FORCE LOAD on TIMER C (this is a STROBE input, there is no data storage, bit 4 will always read back a zero and writing a zero has no effect). 5 TMRC INMODE 1=TIMER C counts positive CNTB transitions, 0=TIMER C counts internal C1MHZ pulses. 6 SPB MODE 1=SERIAL B PORT output mode (CNTB sources shift clock), 0=SERIAL B PORT input mode (external shift clock on CNTB). 7 TODB IN 1=50 Hz operation. C7MHZ divided down by 101339 to generate TODB input of 10 Hz. 0=60 Hz operation. C7MHZ divided down by 102273 to generate TODB input of 10 Hz. CRD (1XF): BIT Bit Name Function (Bits 0-4 of the CRD register operate identically to bits 0-4 of the CRD register, except that functions now apply to TIMER D and bit 1 controls the output of TIMER D on PRD7). 5,6 TIMERD Bits 5 and 6 select one of four input modes for INMODE TIMER D as follows: CRD6 CRD5 0 0 TIMER D counts C1MHz pulses. 0 1 TIMER D counts positive CNTB transitions. 1 0 TIMER D counts TIMERC underflow pulses. 1 1 TIMER D counts TIMERC underflows while CNTB is high. 7 ALARM TODB 1=writing to TODB registers sets ALARM, 0=writing to TODB registers sets TODA clock. C65 Peripheral Control Utilization 6526 cia complex interface adapter #1 keyboard / joystick / paddles / mouse / lightpen / fast serial pra0 keybd output c0 / joystick #1 up / mouse right button pra1 keybd output c1 / joystick #1 down pra2 keybd output c2 / joystick #1 left / paddle "A" fire button pra3 keybd output c3 / joystick #1 right / paddle "B" fire button pra4 keybd output c4 / joystick #1 fire / mouse left button pra5 keybd output c5 / pra6 keybd output c6 / / select port #1 paddles|mouse pra7 keybd output c7 / / select port #2 paddles|mouse prb0 keybd input r0 / joystick #2 up / mouse right button prb1 keybd input r1 / joystick #2 down / paddle "A" fire button prb2 keybd input r2 / joystick #2 left / paddle "B" fire button prb3 keybd input r3 / joystick #2 right prb4 keybd input r4 / joystick #2 fire / mouse left button prb5 keybd input r5 / prb6 keybd input r6 / timer b: toggle/pulse output prb7 keybd input r7 / timer a: toggle/pulse output timer 1 & cra : fast serial timer 2 & crb : tod : sdr : icr : 6526 cia complex interface adapter #2 user port / rs232 / serial bus / VCC bank / NMI pra0 va14 VIC 16K bank select pra1 va15 pra2 rs232 DATA output (C64 mode only) pra3 serial ATN output pra4 serial CLK output pra5 serial DATA output pra6 serial CLK input pra7 serial DATA input prb0 user port / rs232 received data (C64 mode only) prb1 user port / rs232 request to send prb2 user port / rs232 data terminal ready prb3 user port / rs232 ring indicator prb4 user port / rs232 carrier detect prb5 user port prb6 user port / rs232 clear to send prb7 user port / rs232 data set ready timer 1 & cra : rs232 baud rate (C64 mode only) timer 2 & crb : rs232 bit check (C64 mode only) tod : sdr : icr : nmi (/irq) 2.3.6. UART Operation The device contains seven registers to control the different UART modes of operation. Section 2.2 describes how to access these registers. The UART modes can be programmed by accessing the UART control register, URCR, whose bits function as described below. 2.3.6.1. UART Control Register (DRCR) BIT Bit Name Function 0 PARITY EVEN 1 = Even Parity. If parity is enabled, the transmitter will assert the parity bit (P) to a low when "even" parity data is transmitted, otherwise it will pull it high. The receiver checks that the parity bit is asserted, or low, if the data received has even parity; if the bit is not asserted, the device will indicate a parity error. 0=Odd Parity. If parity is enabled, the transmitter will pull the parity bit (P) low when "odd" parity data is transmitted, otherwise it will pull it high. The receiver checks that the parity bit is asserted if the data received has odd parity; if the bit is not asserted when data had odd parity, the device will indicate a parity error. 1 PARITY EN 1 = Parity Enabled. 0 = Parity Disabled. The transmitter and receiver will not allocate a parity bit in the data, instead a stop bit will be used in its place. See the Data Configuration chart below. 2,3 CHAR LENGTH These two bits are used to select the number of bits per character to be transmitted or received. 5, 6, 7 or 8 bits per character may be selected as follows: CH1 CH0 --- --- 0 0 eight bits per character 0 1 seven bits per character 1 0 six bits per character 1 1 five bits per character 4,5 UART MODE These two bits select whether operations will be asynchronous or synchronous for the transmitter and/or receiver. The actual selection is done as follows: DM1 DM0 --- --- 0 0 both transmitter and receiver operate in asynchronous mode. 0 1 receiver operates in synchronous mode, transmitter in asynchronous mode. 1 x receiver operates in asynchronous mode, transmitter in synchronous mode. 6 RCVR EN 0 = Receiver is disabled. 1 = Receiver is Enabled. To provide noise immunity, the duration of a bit interval is segmented into 16 subintervals. This is also used to verify that a high to low transition (START bit) on the RXD line is valid (stays low) at the half point of a bit duration; if not valid, operation will not start. If after an idle period, a high to low transition is detected on the RXD line and is verified to be low, the receiver will synchronized itself to the incoming character for the duration of the character. Received data is then sampled or latched in the center of a bit time to determine the value of the remaining bits. The LSB of the data is the leading bit received. Any unused high order register bits will be set "high". The receiver expects the data to have only one parity bit (when parity is enabled) and one stop bit. At the end of the character reception, the receiver will check whether any errors have occured and will update the status register (URSR) accordingly. In addition, if no errors were encountered the receiver will load the contents of the shift register into the Receiver Data Register, eliminating parity and stop bits. In synchronous mode, the receiver will reconfigure its Data Register and Shift Register so that only 8 data bits are always accepted on the RXD line. This mode only works if an external clock is applied on the PRC2 input line, which is used to shift the bits into the Receiver Shift register. Data on the RXD is latched at the rising edge of the external clock applied in PRC2. 7 XMITR EN 0 = Transmitter is disabled. 1 = Transmitter is Enabled. Transmitter will start operation once the microprocessor writes data to the transmitter data register (DREG), after which the Transmitter Shift Register is loaded and the start bit is placed on the TXD line. The LSB of the data is the leading bit being transmitted. The Transmitter is "doubled buffered" which means that the CPU can load a new character as soon as the previous one starts transmission. This is indicated by the status register, bit 6 (URSR6 -- Empty Data Register), which when set, it indicates that the data register is ready to accept the next character. The character data format is illustrated by figure 1.3. In synchronous mode, the transmitter will reconfigure its Data Register and Shift Register so that only 8 data bits are always transmitted on the TXD line, eliminating all parity and stop bits. The external clock output will be placed in the PRC2 line and will shift the data out of the transmitter shift register. Data on the TXD line will change on the falling edge of the PRC2 signal, the external clock. 2.3.6.2. UART Status Register (URSR) BIT Bit Name Function 0 FULL Receiver Data Register Full bit. This bit is forced to a low upon reset, or after the data register (DREG) is read. This bit is enabled only if the RCVER EN bit is set in the URCR register. The FULL bit is set when the character being received is transferred from the receiver shift register into the receiver data register. If an error is encountered in the character data, this bit will not be set and the proper error bit will be set in the URSR register. 1 OVR Receiver Over-Run Error bit. This bit is cleared upon reset or after reading the receiver data register. This bit is set if the new received charater is attempted to be transferred from the receiver shift register before reading the last character from the data register. Therefore, the last character is preserved in the data register while the new received character is lost. 2 PRTY Receiver Parity Error bit. This bit is cleared upon reset or after reading the receiver data register. The PRTY bit will be set when a parity error is detected on the received character, provided the PARITY EN bit is set and receiver is running asynchronously. 3 FRME Receiver Frame Error bit. This bit is cleared upon reset or after reading the receiver data register. The FRME bit is set whenever the received character contains a low in the first stop-bit slot. 4 IDLE Receiver Idle bit. When this bit is written to a "high", the status register bits 0-3 are disabled until the receiver detects 10 consecutive marks, highs, on the RXD line, at which time the IDLE bit is cleared. This bit is also cleared upon reset. This bit allows the microprocessor, or any external microprocessor device, to ignore the transmission of a character until the start of the next character. 5 ENDT Transmitter End of Transmission bit. This bit is cleared upon reset or whenever data is written into the transmitter data register, DREG. Setting this bit would disable the Transmitter Empty bit, EMPTY, until device completes transmission. 2.3.6.3. Character Configuration ASYNC MODE S T B P = PARITY BIT A I STP = STOP BIT R T T LSB --+ MARK>-+ +---+---+---+---+---+---+---+---+ | P | | D0| D1| D2| D3| D4| P |STP|STP| <-- 5-BIT/CHARACTER | A +---+---+---+---+---+---+---+---+---+ | R | I --+ +---+---+---+---+---+---+---+---+---+ | T | | D0| D1| D2| D3| D4| D5| P |STP|STP| <-- 6-BIT/CHARACTER | Y +---+---+---+---+---+---+---+---+---+---+ | +-> E --+ +---+---+---+---+---+---+---+---+---+---+ | N | | D0| D1| D2| D3| D4| D5| D6| P |STP|STP| <-- 7-BIT/CHARACTER | A +---+---+---+---+---+---+---+---+---+---+---+ | B | L --+ +---+---+---+---+---+---+---+---+---+---+ | E | | D0| D1| D2| D3| D4| D5| D6| D7| P |STP| <-- 8-BIT/CHARACTER | D +---+---+---+---+---+---+---+---+---+---+---+ | --+ --+ --+ +---+---+---+---+---+---+---+ | P | | D0| D1| D2| D3| D4|STP|STP| <-- 5-BIT/CHARACTER | A +---+---+---+---+---+---+---+---+ | R | I --+ +---+---+---+---+---+---+---+---+ | T | | D0| D1| D2| D3| D4| D5|STP|STP| <-- 6-BIT/CHARACTER | Y +---+---+---+---+---+---+---+---+---+ | +-> D --+ +---+---+---+---+---+---+---+---+---+ | I | | D0| D1| D2| D3| D4| D5| D6|STP|STP| <-- 7-BIT/CHARACTER | S +---+---+---+---+---+---+---+---+---+---+ | A | B --+ +---+---+---+---+---+---+---+---+---+---+ | L | | D0| D1| D2| D3| D4| D5| D6| D7|STP|STP| <-- 8-BIT/CHARACTER | E +---+---+---+---+---+---+---+---+---+---+---+ | D --+ CHARACTER CONFIGURATION TABLE 3 2.3.6.4. Register Map C65 UART R/W REG NAME D7 D6 D5 D4 D3 D2 D1 D0 +-----+---+----------+------+------+------+------+------+------+------+------+ | | | | | | | | | | | | | R/W | 0 | DATA | R/X7 | R/X6 | R/X5 | R/X4 | R/X3 | R/X2 | R/X1 | R/X0 | | | | | | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ | | | | | | | | | | | | | READ| 1 | STATUS | XMIT | XMIT | ENDT | IDLE | FRAME|PARITY| OVER | RCVR | | | | | DONE | EMPTY| (R/W)| (R/W)| | | RUN | FULL | +-----+---+----------+------+------+------+------+------+------+------+------+ | | | | | | | | | | R/W | 2 | CONTROL | XMIT | RCVR | UART MODE | WORD LENGTH | PARITY | | | | | ON | ON | | | ON EVEN | +-----+---+----------+------+------+------+------+------+------+------+------+ | | | | | | | | | | | | | R/W | 3 | BAUD LO | BRL7 | BRL6 | BRL5 | BRL4 | BRL3 | BRL2 | BRL1 | BRL0 | | | | | | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ | | | | | | | | | | | | | R/W | 4 | BAUD HI | BRH7 | BRH6 | BRH5 | BRH4 | BRH3 | BRH2 | BRH1 | BRH0 | | | | | | | | | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ | | | | | | | | | | | | | R/W | 5 | INT MASK | XMIT | RCVR | XMIT | RCVR | -- | -- | -- | -- | | | | | IRQ | IRQ | NMI | NMI | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ | | | | | | | | | | | | | READ| 6 | INT FLAG | XMIT | RCVR | XMIT | RCVR | -- | -- | -- | -- | | | | | IRQ | IRQ | NMI | NMI | | | | | +-----+---+----------+------+------+------+------+------+------+------+------+ The BAUD RATE can be generated using the following formulas: URCLK URCLK BaudRate = ---------------- or, COUNT = --------------- - 1 16 x (COUNT+1) 16 x BaudRate Where: COUNT = value loaded into BAUD RATE register URCLK = C7Mhz input, 7.15909 MHz NTSC 7.09375 MHz PAL The following tables show some of the most common data rates. Data rate errors of less than +/-1.5% are acceptable for most purposes. A. NTSC URCLK = 7.15909 MHZ +----+-----------+---------+-----------+---------+ | BR | BAUD RATE | COUNT | BAUD RATE | PERCENT | | # | REQUIRED | (HEX) | OBTAINED | ERROR | +----+-----------+---------+-----------+---------+ | 1 | 50 | 22F4 | 49.999 | .0015 | | 2 | 75 | 174D | 74.999 | .0015 | | 3 | 110 | 0FE3 | 109.991 | .0080 | | 4 | 134.5 | 0CFE | 134.488 | .0090 | | 5 | 150 | 0BA6 | 149.998 | .0015 | | 6 | 300 | 05D2 | 299.895 | .035 | | 7 | 600 | 02E9 | 599.79 | .035 | | 8 | 1200 | 0174 | 1199.58 | .035 | | 9 | 1800 | 00F8 | 1796.96 | .17 | | 10 | 2400 | 00B9 | 2392.74 | .30 | | 11 | 3600 | 007B | 3608.41 | .23 | | 12 | 4800 | 005C | 4811.22 | .23 | | 13 | 7200 | 003D | 7216.82 | .23 | | 14 | 9600 | 002E | 9520.07 | .83 | | 15 | 19200 | 0016 | 19454.0 | 1.323 | | 16 | 31250 | 000D | 31960.2 | 1.023 | (MIDI) | 0 | 56000 | 0007 | 55930.4 | .124 | +----+-----------+---------+-----------+---------+ B. PAL URCLK = 7.09375 MHZ +----+-----------+---------+-----------+---------+ | BR | BAUD RATE | COUNT | BAUD RATE | PERCENT | | # | REQUIRED | (HEX) | OBTAINED | ERROR | +----+-----------+---------+-----------+---------+ | 1 | 50 | 22A2 | 50.001 | .0020 | | 2 | 75 | 1716 | 75.005 | .0080 | | 3 | 110 | 0FBE | 109.987 | .010 | | 4 | 134.5 | 0CDF | 134.514 | .010 | | 5 | 150 | 0B8B | 149.986 | .009 | | 6 | 300 | 05C5 | 299.973 | .009 | | 7 | 600 | 02E2 | 599.75 | .009 | | 8 | 1200 | 0170 | 1198.27 | .144 | | 9 | 1800 | 00F5 | 1802.27 | .126 | | 10 | 2400 | 00B8 | 2396.54 | .144 | | 11 | 3600 | 007A | 3604.55 | .126 | | 12 | 4800 | 005B | 4819.12 | .398 | | 13 | 7200 | 003D | 7150.96 | .68 | | 14 | 9600 | 002D | 9638.25 | .40 | | 15 | 19200 | 0016 | 19276.5 | .40 | | 16 | 31250 | 000D | 31668.5 | 1.01 | (MIDI) | 0 | 56000 | 0007 | 55419.9 | 1.04 | +----+-----------+---------+-----------+---------+ 2.3.7. CPU 2.3.7.1. Introduction The 4502, upon reset, looks and acts like any other CMOS 6502 processor, with the exception that many instructions are shorter or require less cycles than they used to. This causes programs to execute in less time that older versions, even at the same clock frequency. The, stack pointer has been expanded to 16 bits, but can be used in two different modes. It can be used as a full 16-bit (word) stack pointer, or as an 8-bit (byte) pointer whose stack page is programmable. On reset, the byte mode is selected with page 1 set as the stack page. This is done to make it fully 65C02 compatible. The zero page is also programmable via a new register, the "B" or "Base Page" register. On reset, this register is cleared, thus giving a true "zero" page for compatability reasons, but the user can define any page in memory as the "zero" page. A third index register, "Z", has been added to increase flexibility in data manipulation. This register is also cleared, on reset, so that the STZ instructions still do what they used to, for compatibility. This is a list of opcodes that have been added to the 210 previously defined MOS, Rockwell, and GTE opcodes. 1. Branches and Jumps BCC label word-relative BCS label word-relative BEQ label word-relative BMI label word-relative BNE label word-relative BPL label word-relative BRA label word-relative BVC label word-relative BVS label word-relative BSR label Branch to subroutine (word relative) JSR (ABS) Jump to subroutine absolute indirect JSR (ABS,X) Jump to subroutine absolute indirect, X RTN # Return from subroutine and adjust stack pointer 2. Arithmetic Operations NEG A Negate (or 2's complement) accumulator ASR A Arithmetic Shift right accumulator or memory ASR ZP ASR ZP,X INW ZP Increment Word DEW ZP Decrement Word INZ Increment and DEZ Decrement Z register ASW ABS Arithmetic Shift Left Word ROW ABS Rotate Left Word ORA (ZP),Z These were formerly (ZP) non-indexed AND (ZP),Z now are indexed by Z register EOR (ZP),Z (when .Z=0, operation is the same) ADC (ZP),Z CMP (ZP),Z SBC (ZP),Z CPZ IMM Compare Z register with memory immediate, CP2 ZP zero page, and CPZ ABS absolute. 3. Loads, Stores, Pushes, Pulls and Transfers LDA (ZP),Z formerly (ZP) LDZ IMM Load Z register immediate, LDZ ABS absolute, LDZ ABS,X absolute,X. LDA (d,SP),Y Load Accu via stack vector indexed by Y STA (d,SP),Y and Store STX ABS,Y Store X Absolute,Y STY ABS,X Store Y Absolute,X STZ ZP Store Z register (formerly store zero) STZ ABS STZ ZP,X STZ ABS,X STA (ZP),Z formerly (ZP) PHD IMM Push Data Immediate (word) PHD ABS Push Data Absolute (word) PHZ Push Z register onto stack PLZ Pull Z register from stack TAZ Transfer Accumulator to Z register TZA Transfer Z register to Accumulator TAB Transfer Accumulator to Base page register TBA Transfer Base page register to Accumulator TSY Transfer Stack Pointer High byte to Y register and set "byte" stack-pointer mode TYS Transfer Y register to Stack Pointer High byte and set "word" stack-pointer mode 2.3.7.2. CPU Operation The 4502 has the following 8 user registers: A accumulator X index-X Y index-Y Z index-Z B Base-page P Processor status SP Stack pointer PC Program counter Accumulator The accumulator is the only general purpose computational register. It can be used for arithmetic functions add, subtract, shift, rotate, negate, and for Boolean functions and, or, exclusive-or, and bit operations. It cannot, however, be used as an index register. Index X The index register X has the largest number of opcodes pertaining to, or using it. It can be incremented, decremented, or compared, but not used for arithmetic or logical (Boolean) operations. It differs from other index registers in that it is the only register that can be used in indexed-indirect or (bp,X) operations. It cannot be used in indirect-indexed or (bp),Y mode. Index Y The index register Y has the s