From: brain@msen.com (Jim Brain) Subject: CBM Trivia #10 Scores and revised answers Date: 17 Oct 1994 09:17:15 -0400 Organization: Brain Innovations, Inc. Lines: 242 Sender: brain@garnet.msen.com Message-ID: Reply-To: brain@mail.msen.com NNTP-Posting-Host: garnet.msen.com As some may know, I goffed on my answer to $9B, so here is the new, corrected version. The scores have been updated, but it did not change the outcome. So, here are the scores first, followed by the new corrected answers. Please delete older copies of the #10 Answers. (Help stomp out Jim's booboos). Thanks Judging Criteria for Commdore Trivia Edition #10: $090) Motorola 6800 was the only accepted answer. $091) 6501 was the only number accepted. $092) straightforward. $093) straightforward. $094) I accepted none or NOP, or a discussion about SET/CLR flags. $095) straightforward. $096) straightforward. $097) I wasn't that pickey on the exact frequency. Anything arounf 1.02 MHz was accepted. $098) Anything around .98 MHz was accepted. $099) falling or down was accepted. $09A) straightforward. $09B) straightforward. $09C) Anything mentioning this could not be done as written was accpeted. $09D) straightforward. $09E) straightforward. $09F) straightforward. Personal Scoring Table: 0-1 non-CBM owner 2-3 new CBM owner 4-5 GORTEK (where's your microchips?) 6-7 PRG owner 8-9 CBM programmer A-B CBM hacker C-D CBM coder E-F CBM GURU, Jim Butterfield :-) (OK, they are lame, so give me better ones!) With that said, here are the scores: Tarragon Moon 0349CE an131220 0 an131519 035A Philip Zembrod 0389DE Michael Ardai 01239E Udi Finkelstein023469BDE Ojala Pasi 01234789BCE 0621126%BARRYU 34D Stephen Judd 34CE David Wilson 012369CDF Nicolai Plum 13 And the winner is.... Ojala Pasi with 11/16 right. Congratulations to all who entered. The trivia for October should be up already. Jim ----------------------------------------------------------------------------- Here are the answers to Commodore Trivia Edition #10 for September, 1994 Q $090) The 6502 has a rich history. It is modeled after another 8-bit microprocessor. Name the processor. A $090) The 65XX series of processors was modeled after the Motorola 6800. Motorola hampered the design groups' efforts to pursue product developments using the 6800. A core group of 8 designers left Motorola and went to MOS Technologies, which was the largest producer of calculator chips at the time. MOS decided it was time to go into the CPU business. Q $091) The 6502 has a older brother that was never produced. Name its number designation and why it was not produced. A $091) The older brother to the 6502 was the 6501. The 6501 was pin-compatible with the 6800, which prompted a suit by Motorola. Eventually, MOS reached an agreement where they scrapped the 6501 marketing, but were free to market the 6502. Q $092) How many different opcodes are considered valid and "legal" on the MOS NMOS 6502 line? A $092) 151 opcodes are documented in the NMOS 6502 data book. The remaining 105 opcodes were not implemented, and exist as "don't care" states in the opcode matrix. That means that some seemingly invalid opcodes will actually perform pieces of two or more valid opcodes. Newer CPU systems trap all non-implemented opcode usages, but not the 6502. Q $093) Every instruction takes at least __ cycles to complete. Fill in the missing number. A $093) 2. The architecture assumes that each opcode has two bytes in it and one byte can be fetched per cycle. For instructions that use only 1 byte, the extra fetched byte (actually the next opcode), is thrown away. Q $094) Which instructions take more time than necessary as a result of the answer to Q $093? A $094) Although this is a subjective answer, One could nominate NOP on the basis that NOP is generally believed to waste one execution cycle on a particular processor, namely one cycle on the 65XX line. However, one can argue that NOP simply means no operation, and has no ties to length of execution. You be the judge. All other instructions must take at least two cycles: one for opcode fetch, one for operation. Q $095) What did MOS Technologies manufacture befor introducing the 650X line of microprocessors? A $095) As stated above, it was calculator chips. Q $096) Three companies manufactured the 6502 under a cross-licensing agreement. Name them. A $096) Rockwell, MOS Technologies, and Synertek. Q $097) In NTSC-land, how fast does the 1MHz 6510 in the C64 actually run? A $097) 1.022727143 MHz. It is derived by taking the main clock frequency (14.31818MHz) and diving it by 14. Q $098) What about in PAL-land? A $098) 985,248.449 KHz. It is derived by taking the main clock frequency (17.734472MHz) and dividing it by 18. Thus the PAL 64 actually runs slower than the NTSC one. Q $099) Data is latched into the 650X microprocessor on the (rising/falling) edge? A $099) Data is latched in to the 65XX on the falling edge of Phi0 (Phi1). The timing diagram in some books (64 PRG is one) is incorrect. Q $09A) Through the years, the 650X line has changed family numbers, yet the part has not been changed. (A family number is the upper 2 digits in this case) Name the other family numbers used by MOS to denote the 650X line. A $09A) the 75XX line used in the 264 series (Plus/4 and C16), and the 85XX series used in the C64C and C128 series. Q $09B) Consider the following code: ldx #10 lda $ff,x what location does the accumulator get loaded with? A $09B) The answer is location $ff+10 mod 256 = $09. The answer involves explaining a (mis)features of the NMOS 65XX CPU line. The above code instructs the 65XX CPU to use zero-page addressing mode to load the accumulator. In zero-page addressing, the address need only be one byte wide ($ff in this case), because the high byte is considered to be $00. Now, as humans, we would expect the CPU would add 10 to 255 ($ff), giving 265 ($109) as the address to load the accumulator from. However, the CPU designers decided that zero-page addressing means that the high byte will be $00 all the time, no exceptions. If a situation like the above occurs, the low byte of the addition will be used as the low byte of the address (9 in this case), but the high-byte will be ZERO. All zero page addressing modes work this way. Note that the CMOS versions of the 6502 do perform the high byte "fix-up", so this behavior is only seen on the NMOS parts. Q $09C) What about the following? ldx #10 lda ($ff),x A $09C) This was a trick. The code is trying to use INDIRECT INDEXED indexing mode using the x register, but that addressing mode can only be used with the y register. If the code is changed to the following, legal code: ldx #10 lda ($ff),y Then, the above discussion for zero-page addressing holds true here as well. The effective address would have been (hi:lo) $100:$0ff, but is instead (hi:lo) $000:$0ff. The simple rule is: zero page means exactly that. There is no way to address outside of zero-page with zero-page addressing. Q $09D) How many CPU clock signal lines does the 650X require to run? A $09D) 1. The 6501 used two, as the 6800 used two, but the 6502 and successors only required Phi0 (Phi1). Phi2 was generated on the CPU. Q $09E) Where does the 650X line fetch its first byte from after reset? A $09E) $fffc. The address formed by reading $fffd and $fffc is stuffed into the IP, and the code is read starting there. $fffc is read first, since the 65XX line stores addresses in low byte, high byte format. Q $09F) One of the original designers on the NMOS 6502 CPU now heads up Western Design Center in Arizona, and makes the 65C02 and 65C816 CPU chips. Name him. Hint: it is not Chuck Peddle! A $09F) Bill Mensch. He hand-designed these newer parts in the 65XX line in the same manner he and Chuck Peddle and others hand-designed the 6501 and 6502. End of Commodore Trivia Edition #10! Jim Brain brain@mail.msen.com 2306 B Hartland Road Hartland, MI 48353 (810) 737-7300 x8528 -- Jim Brain, Embedded Systems Designer, Brain Innovations. brain@msen.com Dabbling in VR, Old Commodore Computers, and Good Times! "The above views DO reflect my employer, since I am my employer" - Jim Brain