1. DEFINITION 1.1 GENERAL DESCRIPTION The 5717 is a custom CMOS mouse controller for the Commodore 64. It will be housed in the body of a two button mouse, enabling it to be plugged into the 64 joystick port and provide mouse control of GEOS software,etc. It achieves the mouse function by grounding the SID chip's POTX and POTY lines at various times in the SID 512uS cycle to provide the 64 with positional information. 1.2 PIN CONFIGURATION 1. X_QUAD0 INPUT FROM FIRST X DIRECTION PHOTOTRANSISTOR 2. X_QUAD1 INPUT FROM SECOND X DIRECTION PHOTOTRANSISTOR 3. Y_QUAD0 INPUT FROM FIRST Y DIRECTION PHOTOTRANSISTOR 4. Y_QUAD1 INPUT FROM SECOND Y DIRECTION PHOTOTRANSISTOR 5. MBUT INPUT FROM RIGHTMOST MOUSE BUTTON 6. SYNC SYNCCHRONIZATION INPUT FROM SID POTY LINE 7. OSCI INPUT FROM 4MHZ CRYSTAL 8. OSC OUTPUT TO 4MHZ CRYSTAL 9. GND GROUND PIN 10. RESET RESET INPUT, ACTIVE LOW 11. TEST TEST INPUT, DISABLES OSCILLATOR DIVIDER 12. POT_Y OUTPUT TO SID, DECODES Y DIRECTION MOVEMENT 13. POT_X OUTPUT TO SID, DECODES X DIRECTION MOVEMENT 14. J_LEFT OUTPUT TO SID, LEFT JOYSTICK INPUT 15. J_RIGHT OUTPUT TO SID, RIGHT JOYSTICK INPUT 16. J_DOWN OUTPUT TO SID, DOWN JOYSTICK INPUT 17. J_UP OUTPUT TO SID, UP JOYSTICK INPUT 18. VDD +5V POWER PIN 2. FUNCTIONAL DESCRIPTION 2.1 OPERATING MODES AND MODE INITIALIZATION The 5717 supports two different modes of operation:mouse mode and joystick mode. In mouse mode the 4 quadrant inputs are decoded causing the six bit x and y up/down counters to be updated. When the contents of these counters coincide with the SID cycle counter the POTX and POTY outputs are pulled high and remain high until the SID cycle has ended (falling edge of SYNC). The state of the MBUT input will be reflected in the J_UP output(MBUT low -> J_UP low,MBUT high -> J_UP floating). In joystick mode the 5717 enables the mouse to act like a joystick. As in mouse mode the 4 quadrant inputs are decoded to determine movement and direction. The overflow of the SID cycle counter is used to increment the x and y counters until a count of 40 is reached at which time they stop. If during the 40 SID cycles movement is detected the corresponding x or y counter is reset and the corresponding joystick output is held low. If on the other hand no movement is detected during the 40 cycles then a count of 40 is reached and all 4 joystick outputs are disabled(floating). The operating mode of the 5717 is determined during power up. If the MBUT input is held low when reset goes away(rising edge of RESET) then joystick mode is selected, otherwise mouse mode is selected. For test purposes this function is implemented with a transparent latch so that when reset is held low MBUT selects the mode directly. 2.2 TEST FEATURES In normal operation the crystal oscillator runs at 4mhz which is divided down to 1mhz inside the chip. For test purposes this divider can be bypassed by taking the test input high and the OSCI input drives the 5717 logic directly, thereby saving test cycles. 3. ELECTRICAL REQUIREMENTS 3.1 ABSOLUTE MAXIMUM RATINGS Stresses above those listed may cause permanent damage to the circuit. Functional operation of the device at these or any conditions other than those indicated in the operating conditions of this specification is not implied. Exposure to the maximum ratings for extended periods may adversely affect device reliability. characteristic min max units -------------- ----- ----- ------- 3.1.1 ambient temperature under bias -40 +85 deg. C 3.1.2 storage temperature -50 +150 deg. C 3.1.3 applied supply voltage -0.3 +7.0 volts 3.1.4 applied output voltage -0.3 VDD+0.3 volts 3.1.5 applied input voltage -0.3 VDD+0.3 volts 3.1.6 power dissipation - 0.3 watts 3.2 OPERATING CONDITIONS All electrical characteristics are specified over the entire range of the operating conditions unless specifically noted. All voltages are referenced to VSS = 0.0V. characteristic min max units -------------- ----- ----- ------- 3.2.1 supply voltage (VDD) 4.5 5.5 volts 3.2.2 free air temperature 0 +85 deg. C 3.3 DC CHARACTERISTICS characteristic min max units conditions -------------- ----- ----- ----- ---------- 3.3.1 input high level(TEST) 2.0 VDD+0.3 volts - 3.3.2 input low level(TEST) -0.3 0.8 volts - 3.3.3 input high level(OSCI) .7*VDD VDD+0.3 volts - 3.3.4 input low level(OSCI) -0.3 .3*VDD volts - 3.3.5 input high level(X_QUAD0, .8*VDD VDD+0.3 volts - X_QUAD1,Y_QUAD0,Y_QUAD1, MBUT,SYNC,RESET) 3.3.6 input low level(X_QUAD0, -0.3 .2*VDD volts - X_QUAD1,Y_QUAD0,Y_QUAD1, MBUT,SYNC,RESET) 3.3.7 input hysteresis(X_QUAD0, 1.0 - volts - X_QUAD1,Y_QUAD0,Y_QUAD1, MBUT,SYNC,RESET) 3.3.8 input leakage(all inputs -1.0 +1.0 uA 0V<vin<VDD except MBUT,RESET) 3.3.9 input source current 20 100 uA vin=0V (MBUT,RESET) 3.3.10 tristate output leakage -10 +10 uA 0V<vout<VDD (POTX,POTY,J_LEFT,J_RIGHT, J_UP,J_DOWN) 3.3.11 output source current 7.0 - mA vout=VDD-2V (POTX,POTY) 3.3.12 output sink current 5.0 - mA vout=0.4V 3.4 SWITCHING CHARACTERISTICS Switching characteristics are specified for input waveforms switching between 0.4V low level and VDD-0.4V high level and VDD=5.0V. All time measurements of driven signals are referenced to 2.5V on inputs and outputs. characteristic symbol min max units conditions -------------- ------ --- --- ----- ---------- 3.4.1 OSCI cycle time Tcycle 250 1000 nS - 3.4.2 OSCI pulse width high Tpwh 200 - nS - 3.4.3 OSCI pulse width low Tpwl 200 - nS - 3.4.4 POTX/POTY fall after TSYNC-POT 0 200 nS Rpulldown=5.1K SYNC fall mouse mode set Cload=1000pF 3.4.5 POTX/POTY rise after TOSCI-POT 0 200 nS Rpulldown=5.1K OSCI rise mouse mode set Cload=1000pF 3.4.6 MBUT setup time before TMBUTs 50 - ns - rising edge of reset 3.4.7 OSCI rise to output TJr - 200 ns Rpullup=5.1K rise(J_LEFT,J_RIGHT, J_UP,J_DOWN) 3.4.8 OSCI rise to output TJf - 200 ns Rpullup=5.1K fall(J_LEFT,J_RIGHT, J_UP,J_DOWN) 4. MECHANICAL REQUIREMENTS 4.1 MARKING Parts should be marked with Commodore part number, manufacturer's identification and EIA date code. Pin 1 shall be identified. 4.2 The circuit shall be packaged in a standard plastic or ceramic 18 pin DIP with 0.100 inch pin to pin spacing and 0.300 inch pin row to pin row spacing. ---8<----------8<----------8<----------8<----------8<----------8<----------8<---- MOUSE CIRCUIT PINOUT 18 pin plastic package ( .3 in centers ). -------u-------- input | xq0 Vcc | input | xq1 jup | output input | yq0 jdown | output input | yq1 jleft | output input w/pullup | mbut jright | output input w/pullup | sync potx | output osc | xtal2 poty | output osc | xtal1 jbut | output | gnd reset | input w/ pullup ---------------- ---- Xtal oscillator 1 Mhz external crystal for 1 Mhz internal clock. ---- Input charecteristics All inputs shall be schmidt trigger inputs. Please specify to us the charecteritics your arrays can supply. In addition , the reset and mbut inputs will need internal pullups based on what you can supply. ---- Output charecteristics source: 1 ma @ 3.5 v sink: 8 ma @ .5v output timing: Rise time: < 5 us. Fall time < 5 us. Tristate enable time < 5 us. Tristate disblae time < 5 us. NOTE: These incredibly loose times can only hurt your ability to test the part. Since you are going to test them, you'll have to pick times suitable to your test system. ---- Operating temperature range: 0 to 70 degrees C. ---- Operating voltage range: Vcc = 5 volts +/- 10% ---- Current consumption: No spec at this time, but since you are working in CMOS, we anticapate no problems in this area. Let us know what you anticipate the power consumption to be with the clock running, and all outputs unloaded. ---8<----------8<----------8<----------8<----------8<----------8<----------8<---- Explanation of 5717 chip schematic ---------------------------------- Notes: Some inputs are passively pulled to VCC inside the IC. These pullups are NOT shown on the schematic as they were implemented during the layout phase, and during logic design and debug. I/O signals VDD power input for chip. +5 volts. GND power return for chip. 0 volts. TEST normally low input taken high for testing purposes. RESET input used for clocking the chips internal latching of the MBUT input for selecting the mode of operation at power up. This input is low only briefly when the chip is powered up, and remains high until power is removed ( except during testing ). Passive pullup. OSCI Pins for external crystal oscillator. OSC X_QUAD0 Quadrature inputs signals coming from mouse X_QUAD1 optics for the X direction. Y_QUAD0 Quadrature inputs signals coming from mouse Y_QUAD1 optics for the Y direction. SYNC Sync input. See text. MBUT Input for external button. Passively pulled to VCC inside the chip. This input sets the mode of the chip, and is also output by the chip on one of two pins depending one the mode of the chip. J_DOWN Joystick direction open collector type outputs. These J_LEFT outputs are only active when the chip is in joystick J_RIGHT mode. J_UP In joystick mode, this open collector output is asserted when the mouse is moved up. In proportional mode, this output is asserted when the MBUT input is taken low. POT_Y This open drain type of output is asserted only in proportional mode. It is synchronized to the SID conversion cycle, and drives the POT_Y line high at some specific time to cause a specific value to appear in the SID POTY register. The choice of value is based on the mouses Y position in 100ths of an inch MOD 64. POT_X In proportional mode, this line acts just like POT_Y except that the value transmitted on this line reflects the X position of the mouse. In joystick mode, this line is asserted whenever the MBUT signal is asserted. A note about testing: Several gates, and devices in the chip exist solely for the purpose of making the chip easy to test. They are not fully discussed here. Parts: CELL_UDC: This is a special two bit counter cell which may be cascaded, and may count up or down. It is represented as a single cell because certain rules governing CMOS layout make it convenient to do so from the designers standpoint. MUX: Funny Trapezoidal shapes: The are multiplexers. They have one output, a select input, and two data inputs. When select is high, one of the data inputs is gated to the output. When select is low, the other data input is gated to the output. DFF: Little rectangles #119: These are D type flip flops. They have a clock input C, a data input D, and complementary outputs Q and QB. When clock goes from low to high, the value at the D input is latched into the flip flop and appears at output Q. QB is simply the inverted value of Q. GFF: Little rectangles #188. These are latches. They have an gate input G, a data input D, and complementary outputs Q and QB. Whenever the G input is high, the D input is gated through the device and appears at Q and QB. When G is low, the outputs remain in whatever state they were when G was last high. FUNCTIONAL BLOCKS ----------------- Note: Often, a digital signal and its inverse are used. Both contain the exact same information in different embodiments. Often in this text, I will not explicitly list both embodiments as it makes things unclear by cluttering up the text. MASTER CLOCK OSCILLATOR AND DIVIDE DOWN CIRCUIT: This is the logic block in the lower left hand corner of the drawing. This circuit provides two pins for a crystal oscillator. The output of the oscillator is fed to the CLK output from this block after being divided by four. The reset input to this block allows the divide by four counter to be cleared, and the test output allows the divide by four counter to be bypassed altogether. These features are provided strictly for testing purposes. Note that the whole purpose of this block is to provide the nominally 1 MHZ clock to the rest of the chip. MODE SELECTION: The chip has two modes of operation. The mode of the chip is latched in DFF 188 ( lower right ) when the reset input goes from low to high. The reset input has a pullup device internal to the chip, and is normally connected to an external capacitor. When power is applied to the chip, the reset input is held low for a short time by the capacitor which eventually charges up allow reset to go high. The Q output from the chip represents the mode, and that is also fed to an inverter which generates mode bar. When MODEB is high, the chip is configured to be in PROPORTIONAL mode. When MODEB is low, the chip is configured to be in JOYSTICK mode. QUADRATURE SIGNAL CONDITIONING: There are two of these blocks, one for X and Y. They take the three inputs : the two quadrature signals, and a HOLD signal. They turn these into two other signals, a move signal, and a direction signal. The move signal is asserted for one clock period every time a significant mouse movement is detected. Normally these signals come right out of the block as their requisite conditions are detected. The HOLD signal instructs the block to NOT assert the move signal, but to wait until HOLD is no longer asserted. This is needed by other parts of the chip. SYNC DETECTION: The SYNC detection section detects the relevant transition of the SYNC input. ( high to low in the 5717, low to high in the GTE part ). This is done simply by holding the current value of SYNC and its previous value. A single clock pulse is created whenever the correct transition is detected. This pulse is inhibited by the MODE signal when the device is in JOYSTICK mode. 9-bit counter: This is a perversely designed 9 bit up counter ( along the bottom of the schematic ). It consists of two DFFs configured as a ring counter for the lower two bits, and 7 ripple counter stages. It has a carry output which is set whenever the count = 512 ( all ones ). JOYSTICK MODE: In JOYSTICK mode, the counter is free running , and the only relavant output is the CARRY which occurs every half a millisecond ( more or less ). PROPORTIONAL MODE: In pot mode, the counter is cleared every relavant SYNC transition. Thus in POT mode, the counter reflects "what time is it since the last SYNC transition". The count outputs for stages 1 through 5 ( we start at 0 ), are fed to other parts of the chip via the thick black line labeled C(1:5) which is a buss representing 6 lines. The HOLD signal is also derived from this counter. HOLD not only inhibits movement signals from the input conditioning signals, but also indicates to other parts of the chip that "now would be a good time to fire the POT lines if the mouse is in the right position". I.E. the pot lines never fire unless HOLD is asserted. 6 bit counters: The six bit counters each consist of three 2 bit up down counter cells. Each counter has a clear input, a count up input, and a count down input. The counter will only count when the appropriate direction signal is asserted, and a clock occurs. There is some jungle logic driving the clear, up and down signals based on a variety of conditions and the current mode of the chip. JOYSTICK MODE: In this mode the counters only count up. The down signal is therefore inhibited. A NAND gate connected to Y5, and Y3 from each counter detects when the count in the counter is equal to 40. This signal is called FULLBX ( FULLBY ). The UP signal is asserted whenever the CARRY from the 9 bit is asserted, and the counter is not FULL. Therefore the counter will count every .5 MS and stop when the count is 40. This takes twenty milliseconds. The Clear input to the counter is driven whenever movement is detected by the chip. Hence, whenever the mouse moves, the 6 bit counter will be cleared, count to 40 and stop. FULL will therefore be unasserted for 20 MS every time the MOVE signal is asserted. Note that if additional movement is detected before the count reaches 40, the counter will be cleared, hence restarting the 20 MS timer as it were. PROPORTIONAL MODE: In this mode, the counters are never cleared. When movement is detected, either the UP signal, or the DOWN signal is asserted. Thus when the mouse is moved UP(RIGHT) the count is increased by one, and when the mouse is moved DOWN (LEFT) the count is decreased by one. GLUING IT TOGETHER: JOYSTICK MODE: The joystick up signal is asserted whenever the FULL signal is not asserted ( from 6 BIT ) and the direction signal indicates increasing movement ( from the QUADRATURE CONDITIONING ). The joystick down signal is asserted whenever the FULL signal is not asserted ( from 6 BIT ) and the direction signal indicates decreasing movement ( from the QUADRATURE CONDITIONING ). Similar actions are taken by the X section. PROPORTIONAL MODE: EQUALITY DETECTOR: The essence of proportional mode operation is asserting a signal at a time which is a function of the position of the mouse. The output of the equality detector is the YDETECT(XDETECT) signal. The equality detector consists of the 6 XOR gates above each 6bit counter, and the 6 input NAND gate driven by those XOR gates. The output of the NAND gate will fire only when the 6 bit counter value ( mouse position ) is appropriately matched to the 9 bit counter value ( what time it is ). This is an equality detector, but it does not assert when the counts are equal. Its been slightly miswired. The detector will only fire when HOLD is asserted ( that range of time when firing asserting the POT signal would be appropriate ), and when the time is right for the current position. Not equals, just correct. Finally, just before the POT output, there is a DFF which is configured to be set only when the DETECT signal is asserted, and cleared when the proper SYNC transition.